HA-2425 데이터 시트보기 (PDF) - Intersil
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HA-2425 Datasheet PDF : 9 Pages
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HA-2420, HA-2425
Application Information
HOLD STEP VOLTAGE (mV)
+10
INPUT
+IN
-IN
S/H
CONTROL
OUT
OUTPUT
5
-10
-5
0
-5
-10
-15
-20
+5
+10
DC INPUT VOLTAGE (V)
CH = 0.1µF
CH = 10,000pF
CH = 1000pF
-25
-30
CH = 100pF
-35
FIGURE 5. HOLD STEP vs INPUT VOLTAGE
Offset Adjustment
The offset voltage of the HA-2420 and HA-2425 may be
adjusted using a 100kΩ trim pot, as shown in Figure 8. The
recommended adjustment procedure is:
Apply 0V to the sample-and-hold input, and a square wave
to the S/H control.
Adjust the trim pot for 0V output in the hold mode.
Gain Adjustment
The linear variation in pedestal voltage with sample-and- hold
input voltage causes a -0.06% gain error (CH = 1000pF). In
some applications (D/A deglitcher, A/D converter) the gain
error can be adjusted elsewhere in the system, while in other
applications it must be adjusted at the sample-and-hold. The
two circuits shown below demonstrate how to adjust gain error
at the sample-and-hold.
The recommended procedure for adjusting gain error is:
1. Perform offset adjustment.
2. Apply the nominal input voltage that should produce a
+10V output.
3. Adjust the trim pot for +10V output in the hold mode.
4. Apply the nominal input voltage that should produce a
-10V output.
5. Measure the output hold voltage (V-10NOMINAL). Adjust
the trim pot for an output hold voltage of
(---V-----–--1----0----N-----O------M-----I--N-----A----L-----)---+-----(------1---0----V------)
2
RI
RF
0.002RI
S/H CONTROL
INPUT
NOTE: GAIN ~ 1 + R--R---F-I-
FIGURE 7. NON-INVERTING CONFIGURATION
Figure 8 shows a typical unity gain circuit, with Offset Zero-
ing. All of the other normal op amp feedback configurations
may be used with the HA-2420/2425. The input amplifier
may be used as a gated amplifier by utilizing Pin 11 as the
output. This amplifier has excellent drive capabilities along
with exceptionally low switch leakage.
CONTROL
V+
CH
-
+
+
-
IN
V-
OUT
100kΩ
OFFSET TRIM (±25mV RANGE)
FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW)
The method used to reduce leakage paths on the PC board
and the device package is shown in Figure 9. This guard ring
is recommended to minimize the drift during hold mode.
The hold capacitor should have extremely high insulation
resistance and low dielectric absorption. Polystyrene (below
85oC), Teflon, or Parlene types are recommended.
For more applications, consult Intersil Application Note
AN517, or the factory applications group.
CONTROL
GND
-IN
HOLD
CAPACITOR
+IN
RF
0.002RF
INPUT RI
-IN
OUT
OUTPUT
+IN
S/H CONTROL INPUT
S/H
CONTROL
NOTE: GAIN ∼ -–--R-R----IF--
FIGURE 6. INVERTING CONFIGURATION
OUT
V-
V+
FIGURE 9. GUARD RING LAYOUT (BOTTOM VIEW)
5-5
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