QH220 데이터 시트보기 (PDF) - Renesas Electronics
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QH220 Datasheet PDF : 19 Pages
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QHx220
Power ON/OFF Sequence
Power ON
Slope1: >1.8V/50ms
VDDA & VDDA2
Power ON
1.8V
0V
t1>0
ENBAR Low
t2>250µs
BUS ENABLE
Low
CLK Low
DATA Low
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MSB
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
I-DAC
(10 bits: 0111111111)
Q-DAC
(10 bits: 0111111111)
(This command sets QHx220 into minimum gain (Note 8))
Freq. Range Gain Spare
(MTV: 00) (0) (0)
Power OFF
VDDA & VDDA2 1.8V
Power OFF
Slope2: >1.8V/50ms
0V
ENBAR
Low
BUS ENABLE
Low
CLK
Low
DATA
Low
NOTES:
8. When the chip is powered up its register are all zero. This means -135° phase and full analog gain, WLAN Application and 0dB
coarse gain (the boost gain mode is not enabled).
9. VDDA and VDDA2 should be connected on the PCB and decoupled with caps right next to the pin.
10. The SPI Bus is not accessible when VDDA/VDDA2 are <1V.
FN6986 Rev 0.00
October 20, 2009
Page 6 of 19
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