ML6415 데이터 시트보기 (PDF) - Fairchild Semiconductor

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ML6415

S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation

Fairchild Semiconductor 

ML6415

Pin Configuration

ML6415

8-Pin SOIC (S08)

YIN

RF MOD

GND

CIN

1

8

2

7

3

6

4

5

TOP VIEW

YOUT

VCC

CVOUT

COUT

Pin Descriptions

Pin #

1

2

3

4

5

6

7

8

Signal Name

YIN

RF MOD

GND

CIN

COUT

CVOUT

VCC

YOUT

Description

Luminance input

Output to RF modulator driver

Ground

Chrominance input

Chrominance output

Composite video output

5V supply

Luminance output

DATA SHEET

Functional Description

Introduction

This product is a dual monolithic continuous time video filter

designed for reconstructing the luminance and chrominance

signals from an S-Video D/A source. Composite video out-

put is generated by summing the Y and C outputs. The chip

is intended for use in applications with AC coupled input and

AC coupled outputs. (See Figure 1)

The reconstruction filters approximate a 4th-order Butter-

worth characteristic with an optimization toward low over-

shoot and flat group delay. Y, C, and CV outputs are capable

of driving 2Vpp into AC coupled 150Ω video loads, with up

to 35pF of load capacitance at the output pin.

All channels are clamped during sync to establish the appro-

priate output voltage swing range. Thus the input coupling

capacitors do not behave according to the conventional RC

time constant. Clamping for all channels settles to less than

10mv within 5ms of a change in video input sources.

In most applications the input coupling capacitors are 0.1µF.

The Y and C input typically sinks 1µA during active video,

which nominally tilts a horizontal line by about 2mV at the Y

output. During sync, the clamp typically sources 20µA to

restore the DC level. The net result is that the average input

current is zero.

Any change in the input coupling capacitor’s value will

inversely alter the amount of tilt per line. Such a change will

also linearly affect the clamp response times.

This product is robust and stable under all stated load and

input conditions. Capacitive bypassing VCC directly to

ground ensures this performance.

Luminance (Y) I/O

The luma input is driven by either a low impedance source of

1VP-P or the output of a 75Ω terminated line. The input is

required to be AC coupled via a 0.1µF coupling capacitor

which allows for a settling time of 5ms. The luma output is

capable of driving an AC coupled 150Ω load at 2Vpp, or

1Vpp into a 75Ω load. Up to 35pF of load capacitance

(at the output pin) can be driven without stability or slew

issues. The output is AC coupled with a 400µF or larger AC

coupling capacitor.

2

REV. 2F May 2003

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