22346UFVZ 데이터 시트보기 (PDF) - Renesas Electronics
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22346UFVZ
Renesas Electronics
22346UFVZ Datasheet PDF : 16 Pages
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ISL22346
Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 21) (Note 5) (Note 21)
VCCRamp VCC Ramp Rate
tD
Power-up Delay
0.2
VRCegCisatbeor vreecValpl ocro,mtopDleCtePd,InaintidalI2VCalIuneterface
3
in standby state
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
EEPROM Retention
Temperature T < +55°C
50
tWC
Non-volatile Write Cycle Time
(Note 19)
12
20
SERIAL INTERFACE SPECIFICATIONS
VIL
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
-0.3
0.3*VCC
VIH
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
0.7*VCC
VCC + 0.3
Hysteresis SDA and SCL Input Buffer Hysteresis
VOL
SDA Output Buffer LOW Voltage,
Sinking 4mA
0.05*VCC
0
0.4
Cpin A2, A1, A0, SHDN, SDA, and SCL Pin
10
(Note 20) Capacitance
fSCL
SCL Frequency
400
tsp
Pulse Width Suppression Time at
Any pulse narrower than the max spec is
50
SDA and SCL Inputs
suppressed
tAA
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until
900
Valid
SDA exits the 30% to 70% of VCC window
tBUF
Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of VCC
during the following START condition
1300
tLOW
tHIGH
tSU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
tHD:STA START Condition Hold Time
tSU:DAT Input Data Setup Time
tHD:DAT Input Data Hold Time
Measured at the 30% of VCC crossing
Measured at the 70% of VCC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
1300
600
600
600
100
0
tSU:STO
tHD:STO
tDH
STOP Condition Setup Time
STOP Condition Hold Time for Read,
or Volatile Only Write
Output Data Hold Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
600
1300
0
tR
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
250
0.1*Cb
UNIT
V/ms
ms
Cycles
Years
ms
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FN6177 Rev 2.00
September 3, 2009
Page 6 of 16
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