IS42S16100-5TL 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS42S16100-5TL

512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Silicon Solution 

IS42S16100

PIN CONFIGURATION

package code: B 60 bALL fbga (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)

1234567

A

VSS DQ15

B

DQ14 VSSQ

C

DQ13 VDDQ

D

DQ12 DQ11

E

DQ10 VSSQ

F

DQ9 VDDQ

G

DQ8 NC

H

NC NC

J

NC UDQM

K

NC CLK

L

CKE NC

M

A11 A9

N

A8 A7

P

A6 A5

R

VSS A4

PIN DESCRIPTIONS

A0-A10

Row Address Input

A0-A7

Column Address Input

A11

Bank Select Address

DQ0 to DQ15 Data I/O

CLK

System Clock Input

CKE

Clock Enable

CS

Chip Select

RAS

Row Address Strobe Command

CAS

Column Address Strobe Command

DQ0 VDD

VDDQ DQ1

VSSQ DQ2

DQ4 DQ3

VDDQ DQ5

VSSQ DQ6

NC DQ7

VDD NC

LDQM WE

RAS CAS

NC CS

NC NC

A0 A10

A2 A1

A3 VDD

WE

LDQM, UDQM

Vdd

Vss

Vddq

Vssq

NC

Write Enable

x16 Input/Output Mask

Power

Ground

Power Supply for I/O Pin

Ground for I/O Pin

No Connection

2

Integrated Silicon Solution, Inc. — www.issi.com

Rev.  D

01/28/08

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