CXD2312R
Digital Output
The following table shows the correlation between the analog input voltage and the digital output code
(TESTMODE = 1, LINV, MINV = 0)
Input signal voltage
Step
Digital output code
MSB
LSB
VRT
0
111111111
255
100000000
256
011111111
VRB
511
000000000
The following table shows the output state for the combination of TESTMODE, LINV, and MINV states.
TESTMODE LINV MINV D0 D1 D2 D3 D4 D5 D6 D7 D8
1
0
0 PPPPPPPPP
1
1
0 NNNNNNNNP
1
0
1 PPPPPPPPN
1
1
1 NNNNNNNNN
0
0
0 010101010
0
1
0 101010100
0
0
1 010101011
0
1
1 101010101
P: Forward-phase output N: Inverted output
Timing Chart 1
tPW1
tPW0
Clock
1.65V
Analog input
Data output
tSH
tSL
HOLD N
HOLD N + 1
tDL
N–3
N–2
HOLD N + 2
HOLD N + 3
N–1
N
Timing Chart 2
Output enable (OE)
1.65V (DVDD = 3.3V)
2.5V (DVDD = 5.0V)
tPEZ
1.65V
tPZE
1.65V (DVDD = 3.3V)
2.5V (DVDD = 5.0V)
1.65V
Data output
Active
High Impedance
–6–
Active