DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

CXD1961AQ 데이터 시트보기 (PDF) - Sony Semiconductor

부품명
상세내역
제조사
CXD1961AQ
Sony
Sony Semiconductor Sony
CXD1961AQ Datasheet PDF : 33 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CXD1961AQ
Functional Description
(1) A/D Converters
The CXD1961AQ has dual 6 bit A/D converters to quantize the analog baseband I/Q signal. The sampling rate
is two times the symbol rate. The input range is determined by the external resisters. See reference circuit (1).
The DC offset cancellation function is set by setting CPU I/F register 1E,1F(hex).
(2) Clock Recovery Circuit
The CXD1961AQ can operate at multiple symbol rates between 20 to 30MSPS. Initial sampling clock
frequency is set by a 24 bit control word via CPU I/F register 18, 19, 1A (hex). This control word is written to
the numerically controlled oscillator (NCO). The internal clock recovery loop feeds clock error data to the
above NCO to provide sampling timing correction. The relation between the symbol rate and the control word
is;
(symbol rate) = 4 × NCO [23:0] × Fcrystal ÷ 224 (Hz)
where NCO [23:0] is the 24 bit control word and Fcrystal is crystal frequency (Hz).
The clock recovery loop coefficient and the loop gain are set by setting CPU I/Fregister 0C (hex) accordingly.
See reference circuit (2). The recovered symbol clock can be monitored at Pin 69.
There are three internal sub-registers to save the NCO control word. By setting the number of the preset sub-
register, the control word corresponded to the certain symbol rate is set to the internal NCO. Contents of the
sub-register are deleted by power off or reset by pin 22. Refer to the explanation of CPU I/F register 0D (hex).
(3) Carrier Recovery Circuit
Any carrier frequency offset which remains on the analog baseband I/Q input is compensated by the internal
digital costas loop. The capture range is ±Rs/8 (Rs: symbol rate). When the carrier capture is performed,
QPSK lock flag QSYNC goes high. QSYNC is output at Pin 82 and CPU I/F register 09 (hex). In QPSK
synchronization, the carrier offset estimation value is output at CPU I/F register 02 (hex) as AFC [7:0]. The
frequency offset is;
(carrier offset) = Rs × AFC [7:0] ÷ 512 (Hz)
where AFC7 is the sign bit that represents the direction of the offset.
(4) Nyquist Roll off Filter
The Nyquist roll off filter for each channel are embedded. The roll off factor is 0.35.
–3–

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]