CXD1961AQ 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD1961AQ

DVB-S Frontend IC (QPSK demodulation + FEC)

Sony Semiconductor 

CXD1961AQ

(10) CPU Interface

The CXD1961AQ has an I2C bus interface. Serial clock SCL is Pin 58 and serial data in out SDA is Pin 59.

Slave address is "1101 111" (DChex).

<Write data>

During the write operation, the second byte is input as the sub-address of the start position. The third byte then

forms the data to be written to the start register. Successive data bytes are written to the successive sub-

address registers up to 21 (hex). Note that registers of sub-addresses 00 (hex) to 0B (hex) are read only.

Slave address

1101 111

0

Sub address

N (hex)

Input data for

sub-address

N (hex)

Input data for

sub-address

N + 1 (hex)

···

STA: start condition

STP: stop condition

ACK: acknowledge

XACK: no acknowledge

<Read operation>

Before the read operation, the sub-address of the start register to be read is input by using write operation, and

terminated with a stop condition. Read operation then begins with the second byte which is the data of the start

register. Data of the successive sub-address registers are read successively following the second byte. All

registers can be read.

Slave address

1101 111

0

Sub address

N (hex)

Slave address

1101 111

1

Output data for

sub-address

N (hex)

Output data for

sub-address

N + 1 (hex)

···

Both SCL and SDA have 5V input capability.

–5–

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