CXD2443Q 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2443Q

Timing Generator for LCD Panels

Sony Semiconductor 

CXD2443Q

Input Signal Protocol

1. Horizontal sync signal

• A double-speed HSYNC or standard HSYNC (or CSYNC) should be input for NTSC and PAL display modes.

Double-speed HSYNC and standard HSYNC input switching is set by the serial data (SNSL).

Note) The double-speed HSYNC should have a cycle and width 1/2 that of the standard HSYNC.

• The signal obtained by cutting off only the bottom of the ternary SYNC should be input for HD display mode.

• The input sync signal polarity is not fixed, and is set by the serial data (HPOL).

• When using the built-in line double-speed controller, set serial data SNSL to Low. The built-in line double-

speed controller supports only the standard HSYNC (or CSYNC).

2. Vertical sync signal

• A normal-speed VSYNC (or CSYNC) should be input for NTSC and PAL display modes.

• A VSYNC that has been sync separated by SYNC SEP. should be input for HD display mode.

• The input sync signal polarity is not fixed, and is set by the serial data (VPOL).

• The phase relationship between HSYNC and VSYNC is specified as follows for the CXD2443Q.

(1) Double-speed NTSC

Double-speed HSYNC

VSYNC Sync signal phase

reference

(2) Double-speed PAL

Double-speed HSYNC

VSYNC Sync signal phase

reference

(3) NTSC (CSYNC input)

ODD FIELD

CSYNC

EVEN FIELD

CSYNC

Sync signal phase reference

(4) PAL (CSYNC input)

ODD FIELD

CSYNC

EVEN FIELD

CSYNC

Sync signal phase reference

(5) HD

ODD FIELD

HSYNC

VSYNC

EVEN FIELD

HSYNC

Sync signal phase

reference

VSYNC

Sync signal phase

reference

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