CXD2443Q 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2443Q

Timing Generator for LCD Panels

Sony Semiconductor 

CXD2443Q

Serial settings during power on

The CXD2443Q should be forcibly reset during power on using the XCLR pin. After being forcibly reset, the

master clock for the CXD2443Q is supplied from CKI3. The initial serial data after power on is loaded to the

CXD2443Q using the clock from CKI3.

Serial settings during PLL free running

When the PLL is in free running status, the serial clock cycle (F ns) may be less than F ≥ 2T with respect to the

master clock cycle (T ns). Take care that the serial clock cycle setting is such that F ≥ 2T during PLL free

running.

Each control data is described in detail below.

(A) H-POSITION

(HP1, HP2, HP3, HP4, HP5, HP6, HP7, HP8)

These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment of

up to ±128 dots is possible with respect to the design center value. (data: 8 bits)

Design center value HP1 HP2 HP3 HP4 HP5 HP6 HP7 HP8

L L L L L L LH

MODE

NTSC (4:3)

NTSC (16:9)

PAL (4:3)

PAL (16:9)

HD

Variable time (±128fH)

±2.8µs

±2.1µs

±2.7µs

±2.0µs

±1.9µs

(B) V-POSITION

(VP1, VP2, VP3, VP4)

These bits set the vertical display start position. The minimum adjustment width is 1H, and adjustment of up to

±8H is possible with respect to the design center value. (data: 4 bits)

Design center value VP1 VP2 VP3 VP4

L L LH

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