DG9425 데이터 시트보기 (PDF) - Vishay Semiconductors

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DG9425

Low Voltage, Dual Supply, Low RON, Quad SPST Analog Switches

Vishay Semiconductors 

www.vishay.com

SCHEMATIC DIAGRAM (typical channel)

V+

DG9424, DG9425, DG9426

Vishay Siliconix

VL

S

Level

VIN

Shift/

Drive

D

GND

V-

TEST CIRCUITS

Fig. 1

VL

V+

VL

V+

NO or NC

VIN

COM

IN

GND

V-

RL

300 Ω

VOUT

CL

35 pF

Logic

Input

VINH

VINL

VOUT

Switch

0V

Output

50 %

tr < 5 ns

tf < 5 ns

tOFF

90 %

0.9 x VOUT

tON

V-

Switch

CL (includes fixture and stray capacitance)

VOUT = VIN

RL

RL + rON

Note: Logic input waveform is inverted for switches that

have the opposite logic sense control

Fig. 2 - Switching Time

VL

VIN1

VIN2

NO1

IN1

NC2

IN2

GND

V+

COM1

VO1

COM2

VO2

RL1

300 Ω

CL1

35 pF

V-

RL2

300 Ω

CL2

35 pF

Logic

Input

Switch

Output

3V

0V

VIN1

VO1

0V

VIN2

VO2

Switch

0V

Output

50 %

90 %

90 %

tD

tD

V-

CL (includes fixture and stray capacitance)

Fig. 3 - Break-Before-Make (DG9426)

S16-0453-Rev. H, 21-Mar-16

9

Document Number: 71807

For technical questions, contact: analogswitchtechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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