ATMEGA32(2008) 데이터 시트보기 (PDF) - Atmel Corporation

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ATMEGA32
(Rev.:2008)

8-bit Microcontroller with 32K Bytes In-System Programmable Flash

Atmel Corporation 

Data Memory Access

Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clkCPU cycles as described in Figure 10.

Figure 10. On-chip Data SRAM Access Cycles

T1

T2

T3

clk

CPU

Address

Data

WR

Data

RD

Compute Address

Address Valid

Memory Access Instruction

Next Instruction

EEPROM Data

Memory

EEPROM Read/Write

Access

The ATmega32 contains 1024 bytes of data EEPROM memory. It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an endurance of at

least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described

in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and

the EEPROM Control Register.

“Memory Programming” on page 256 contains a detailed description on EEPROM Programming

in SPI, JTAG, or Parallell Programming mode.

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets

the user software detect when the next byte can be written. If the user code contains instructions

that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC

is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time

to run at a voltage lower than specified as minimum for the clock frequency used. See “Prevent-

ing EEPROM Corruption” on page 22 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

18 ATmega32(L)

2503N–AVR–06/08

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