SL23EP08SI-4T 데이터 시트보기 (PDF) - Silicon Laboratories
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SL23EP08SI-4T Datasheet PDF : 15 Pages
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SL23EP08
AC Electrical Specifications: VDD=3.3V+/-10% and 0°C to +70°C Operation (Commercial Grade)
Symbol Description
Condition
Min Typ Max Unit
FOUT-1 Output Frequency
CL=30pf, All devices
10
-
160 MHz
FOUT-2 Output Frequency
CL=20pF, -1H and -5H versions
10
-
220 MHz
FOUT-2 Output Frequency
CL=15pF, -1,-2,-3 and -4 versions
10
-
200 MHz
DC-1
Duty Cycle. -1, -2, -3,-4,-1H CL=30pF, FOUT=66.6MHz and Measured 40.0 50.0 60.0
%
and -5H versions
at VDD/2
DC-2
Duty Cycle, -1, -2, -3,-4,-1H CL=15pF, FOUT<66.6MHz and Measured 45.0 50.0 55.0
%
and -5H versions
at VDD/2
DC-1
Duty Cycle. -1, -2, -3,-4,-1H CL=30pF, FOUT=120MHz and Measured
TBD
TBD
TBD
%
and -5H versions
at VDD/2
DC-2
Duty Cycle. -1, -2, -3,-4,-1H CL=15pF, FOUT=120MHz and Measured
TBD
TBD
TBD
%
and -5H versions
at VDD/2
tr/f-1
Rise and Fall Times. -1, -2, - Measured between 0.8V and 2.0V
3, and -4 versions
CL=30pF
-
1.6
ns
-
tr/f-2
Rise and Fall Times. -1, -2, - Measured between 0.8V and 2.0V
3, and -4 versions
CL=15pF
-
1.2
ns
-
tr/f-3
Rise and Fall Times. -1,1H Measured between 0.8V and 2.0V
and -5H versions
CL=30pF
-
1.2
ns
-
tr/f-3
Rise and Fall Times. -1H and Measured between 0.8V and 2.0V
-5H versions
CL=15pF
-
1.0
ns
-
Output-to-Output on same
SKW-1 bank A or B. All versions
All outputs are equally loaded. Measured
at VDD/2
-
150
60
ps
SKW-2
SKW-3
SKW-4
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Device-to-Device Skew.
All versions
All outputs are equally loaded. Measured
at VDD/2
All outputs are equally loaded. Measured
at VDD/2
All outputs are equally loaded. Measured
at VDD/2 and FBK pin
150
-
60
ps
300
-
130
ps
500
-
180
ps
tCFD
CLKIN to FBK Rising Edge All outputs are equally loaded. Measured
Delay
-200
-
at VDD/2
200
ps
t2
Delay Time, CLKIN Rising PLL Bypass mode
Edge to CLKOUT Rising
Edge[2]
PLL enabled @ 3.3V
1.5
–
–100
–
4.4
ns
100
ps
(Measured at VDD/2)
PLL enabled @2.5V
–200
–
200
ps
t3
Part-to-Part Skew[2]
(Measured at VDD/2)
tLOCK PLL Lock Time
Measured at VDD/2. Any output to any
output, 3.3V supply
Measured at VDD/2. Any output to any
output, 2.5V supply
Valid on all clock pins from VDD=2.97V
±150 ps
–
–
±300 ps
–
–
-
-
1.0
ms
Rev 1.0, May 18, 2006
Page 7 of 15
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