AS5SS256K18 데이터 시트보기 (PDF) - Micross Components

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AS5SS256K18

256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through

Micross Components 

SSRAM

AS5SS256K18

CLK

ADSP\

ADSC\

ADDRESS

BEW\,

BWa\ - BWb\

GW\

CE\

(NOTE 2)

ADV\

OE\

D

Q

tKC

tKL

WRITE TIMING

tADSS

tKH

tADSH

ADSC\ extends burst. tADSS

tAS

A1

tAH

A2

BYTE WRITE signals are ignored

when ADSP\ is LOW.

tADSH

A3

tWS tWH

(Note 5) tWS tWH

tCES tCEH

tAAS tAAH

High-Z

(Note 3)

tDS tDH

D(A1)

tOEHZ

(Note 4)

ADV\ suspends burst.

D(A2) D(A2+1) D(A2+1)

(Note 1)

D(A2+2) D(A2+3)

D(A3)

D(A3+1)

D(A3+2)

BURST READ SINGLE WRITE

BURST WRITE

Extended

BURST WRITE

Don’t Care

NOTE: 1. D(A2) refers to output from address A2. D(A2+1) refres to output from the next internal burst address following A2.

2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.

3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period

prior to the byte write enable inputs being sampled.

4. ADV\ must be HIGH to permit a WRITE to the loaded address.

5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BWE\, BWa\ and BWb\ LOW.

AS5SS256K18

Rev. 2.5 10/13

10

Micross Components reserves the right to change products or specifications without notice.

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