AS5SS256K18 데이터 시트보기 (PDF) - Micross Components
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AS5SS256K18 Datasheet PDF : 14 Pages
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SSRAM
AS5SS256K18
TRUTH TABLE
OPERATION
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
ADDRESS
USED
CE\ CE2\ CE2 ZZ ADSP\ ADSC\ ADV\ WRITE\ OE\ CLK
DQ
NONE
H X XL X
L
X
X
X L-H High-Z
NONE
L X LL L
XX
X
X L-H High-Z
NONE
L H XL L
XX
X
X L-H High-Z
NONE
L X LL H
L
X
X
X L-H High-Z
NONE
L H XL H
L
X
X
X L-H High-Z
NONE
X X XH X
XX
X
X X High-Z
EXTERNAL L L H L L
XX
X
L L-H Q
EXTERNAL L L H L L
XX
X
H L-H High-Z
EXTERNAL L L H L H
L
X
L
X L-H D
EXTERNAL L L H L H
L
X
H
L L-H Q
EXTERNAL L L H L H
L
X
H
H L-H High-Z
NEXT
X X XL H
H
L
H
L L-H Q
NEXT
X X XL H
H
L
H
H L-H High-Z
NEXT
H X XL X
H
L
H
L L-H Q
NEXT
H X XL X
H
L
H
H L-H High-Z
NEXT
X X XL H
H
L
L
X L-H D
NEXT
H X XL X
H
L
L
X L-H D
CURRENT X X X L H
HH
H
L L-H Q
CURRENT X X X L H
HH
H
H L-H High-Z
CURRENT H X X L X
HH
H
L L-H Q
CURRENT H X X L X
HH
H
H L-H High-Z
CURRENT X X X L H
HH
L
X L-H D
CURRENT H X X L X
HH
L
X L-H D
NOTES: 1. X means “Don’t Care.” \ means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\) and BWE\ are LOW or GW\ is LOW. WRITE\ = H for all BWx\,
BWE\, GW\ HIGH.
3. BWa\ enables WRITEs to DQas and DQPa. BWb\ enables WRITEs to DQbs and DQPb.
4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH throughout the input
data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals
and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification.
AS5SS256K18
Rev. 2.5 10/13
Micross Components reserves the right to change products or specifications without notice.
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