USB3300-EZK(2005) 데이터 시트보기 (PDF) - SMSC -> Microchip
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USB3300-EZK Datasheet PDF : 11 Pages
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Hi-Speed USB Host or Device PHY with ULPI Low Pin Interface
Table 1 USB3300 Pin Definitions (continued)
DIRECTION, ACTIVE
PIN
NAME
TYPE
LEVEL DESCRIPTION
17
DATA[7]
18
DATA[6]
I/O,
CMOS,
Pull-low
I/O,
CMOS,
Pull-low
N/A 8-bit bi-directional data bus. Bus ownership is
determined by DIR. The Link and PHY initiate data
transfers by driving a non-zero pattern onto the data
bus. ULPI defines interface timing for a single-edge
N/A data transfers with respect to rising edge of
CLKOUT. DATA[7] is the MSB and DATA[0] is the
LSB.
19
DATA[5]
I/O,
N/A
CMOS,
Pull-low
20
DATA[4]
I/O,
N/A
CMOS,
Pull-low
21
DATA[3]
I/O,
N/A
CMOS,
Pull-low
22
DATA[2]
I/O,
N/A
CMOS,
Pull-low
23
DATA[1]
I/O,
N/A
CMOS,
Pull-low
24
DATA[0]
I/O,
N/A
CMOS,
Pull-low
25
VDD3.3
Power
N/A A 0.1uF bypass capacitor should be connected
between this pin and the ground plane on the PCB.
26
VDD1.8
Power
N/A 1.8V Digital regulator bypass. A 4.7uF low ESR
ceramic bypass capacitor should be connected
between this pin and the ground plane of the PCB.
This pin should be connected to the other VDD1.8,
pin 15.
27
XO
Output,
Analog
N/A Crystal pin. If using an external clock on XI this pin
should be floated.
28
XI
Input,
Analog
N/A Crystal pin. A 24MHz crystal is supported. The
crystal is placed across XI and XO. An external
24MHz clock source may be driven into XI in place
of a crystal.
29
VDDA1.8
Power
N/A 1.8 Volt Analog Regulator bypass. A 4.7uF low ESR
ceramic bypass capacitor to the ground plane of the
PCB is recommended.
30
VDD3.3
Power
N/A Analog 3.3 volt supply. A 0.1uF low ESR bypass
capacitor connected to the ground plane of the PCB
is recommended.
31
VDD3.3
Power
N/A Analog 3.3 volt supply. Should be connected directly
to pin 30.
32
RBIAS
Analog,
CMOS
N/A External 12KΩ +/- 1% bias resistor to ground.
Revision 1.02 (02-16-05)
8
PRODUCT PREVIEW
SMSC USB3300
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