LD3985 데이터 시트보기 (PDF) - STMicroelectronics

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LD3985

ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REGULATORS LOW ESR CAPACITORS COMPATIBLE

STMicroelectronics 

LD3985 SERIES

Figure 2: Connection Diagram (top view for SOT and TSOT, top through view for Flip-Chip)

TSOT23-5L/SOT23-5L

Flip-Chip

Table 4: Pin Description

Pin N°

SOT23-5L/

TSOT23-5L

1

2

3

Pin N°

Flip-Chip

4

2

1

4

5

5

3

Symbol

Name and Function

VI

GND

VINH

BYPASS

VO

Input Voltage of the LDO

Common Ground

Inhibit Input Voltage: ON MODE when VINH ≥ 1.2V, OFF MODE when VINH ≤

0.4V (Do not leave floating, not internally pulled down/up)

Bypass Pin: Connect an external capacitor (usually 10nF) to minimize noise

voltage

Output Voltage of the LDO

Figure 3: Typical Application Circuit

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