LH532100B-1 데이터 시트보기 (PDF) - Sharp Electronics
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LH532100B-1 Datasheet PDF : 8 Pages
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CMOS 2M MROM
LH532100B-1
A17 30
A16 2
A15 3
A14 29
A13 28
A12 4
A11 25
A10 23
A9 26
A8 27
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
MEMORY
MATRIX
(262,144 x 8)
COLUMN SELECTOR
SENSE AMPLIFIER
CE 22
CE
BUFFER
TIMING
GENERATOR
OE1/OE1/DC 1
OE/OE 24
OE
BUFFER
OUTPUT BUFFER
32 16
VCC GND
13 14 15 17 18 19 20 21
D0 D1 D2 D3 D4 D5 D6 D7
NOTE: Pin numbers apply to the 32-pin DIP, SOP, QFJ, or TSOP (Type II).
Figure 5. LH532100B-1 Block Diagram
532100B1-4
PIN DESCRIPTION
SIGNAL
PIN NAME
NOTE
SIGNAL
PIN NAME
NOTE
A0 – A17
Address input
D0 – D7
Data output
CE
Chip enable input
OE/OE
Output enable input
1
OE1/OE1/DC Output enable input
1, 2
VCC
Power supply (+5 V)
GND
Ground
NOTES:
1. Active levels of OE/OE and OE1/OE1/DC are mask-programmable. Selecting DC allows the outputs to be active for both high and low levels
applied to this pin. It is recommended to apply either a HIGH or a LOW to the DC pin.
2. DC = Don’t care.
3
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