Fig 6 : Sync Timing::625/50 Interlaced System in Master Mode
sub-address71[7] =0
Fsync
Vsync
Hsync
Fsync polarity
sub-address71[3]
Vsync polarity
sub-address71[4]
CSYNC
621 622 623 624 625 1 2 3 4 5 6 7 8 9
21 22 23
Fsync
Vsync
Hsync
CSYNC
309 310 311 312 313 314 315 316 317 318 319 320 321
334 335
Fig 7 : Sync Timing::525/60 Non-interlaced System in Master Mode
Fsync
Fsync polarity
sub-address71[3]
sub-address71[7] =1
Vsync
Hsync
Vsync polarity
sub-address71[4]
CSYNC
261 262 1 2 3 4 5 6 7 8 9 10 11
21 22 23
Fig 8 : Sync Timing::625/50 Non-interlaced System in Master Mode
sub-address71[7] =1
Fsync
Vsync
Hsync
Fsync polarity
sub-address71[3]
Vsync polarity
sub-address71[4]
CSYNC
308 309 310 311 312 1 2 3 4 5 6 7 8 9
21 22 23
No. 8
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.