M64898GP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M64898GP Datasheet PDF : 8 Pages
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MITSUBISHI ICs (TV)
M64898GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC
DESCRIPTION OF PIN
Pin No.
Symbol
Pin name
1
f in
Prescaler input
2
GND
GND
3
V CC1
Power supply voltage 1
4
V CC2
Power supply voltage 2
5
BS4
6
BS3
Band switching
7
BS2
outputs
8
BS1
9
VDC
DC-DC power
supply voltage
10
Ipk
Peack current
detect
11
SWE
Switching output
12
+B
Power supply
voltage
13
Vtu
Tuning output
14
Vin
Filter input
(Charge pump output)
15
LD/ftest
Lock detect /Test port
16
CONT
17
CLOCK
18
DATA
19
ENABLE
20
X in
fREF Switchi
Clock input
Data input
Enable input
This is connected to
the crystal oscillator.
Function
Input for the VCO frequency.
Ground to 0V.
Power supply voltage terminal. 5.0V±0.5V
Power supply for band switching, Vcc1 to 10V
PNP open collector method is used.
When the band switching data is "H", the output is ON.
When it is "L", the output is OFF.
DC-DC power supply voltage terminal. 5.0V±0.5V
When potential difference with VDC terminal becomes more than 0.33V by current
limiting detector of DC-DC converter, the listing rises with off.
DC-DC converter oscillator output.
Power supply voltage for turning voltage.
This supplies the tuning voltage.
This is the output terminal for the LPF input and charge pump output. When the phase
of the programmable divider output (f 1/N) is ahead compared to the reference
frequency (fREF), the "source" current state becomes active.
If it is behind, the "sink" current becomes active.
If the phases are the same, the high impedance state becomes active.
Lock detector output. When loop of phase locked loop locked it, it rises with "H" level
in "L" level or unlock.
In control byte data input, the programmabule freq. divider output and reference freq.
output is selected by the test mode.
Set up reference frequency divider ratio.
In "L" level, set it up in 1/640(19Bit) in setting "opening" in 1/1024(19Bit) or 1/512
(18Bit).
Data is read into the shift register when the clock signal falls.
Input for band SW and programmable freq. divider set up.
This is normally at a "L". When this is at "H", data and clock signals are received. Data
is read into the latch when the enable signal after the 18th signal of the clock signal
falls or when the 19th pulse of the clock signal falls.
4.0MHz crystal oscillator is connected.
ABSOLUTE MAXIMUM RATINGS (Ta=-20°C to +75°C, unless otherwise noted)
Symbol
V CC1
VCC2
VI
VO
VBSOFF
IBSON
tBSON
Pd
Topr
Tstg
Parameter
Supply voltage 1
Supply voltage 2
Input voltage
Output voltage
Voltage applied when
the band output is OFF
Band output current
ON the time when the
band output is ON
Power dissipation
Operating temperature
Storage temperature
Conditions
Pin3
Pin4
Not to exceed Vcc1
fREF output
per 1 band output circuit
40mA per 1 band output circuit
3circuits are pn at same time,
Ta=75°C
Ratings
Unit
6.0
V
10.8
V
6.0
V
6.0
V
10.8
V
40.0
mA
10
sec
255
mW
-20 to +75
°C
-40 to +125
°C
2
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