M64898GP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M64898GP

PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC

MITSUBISHI ELECTRIC  

MITSUBISHI ICs (TV)

M64898GP

PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC

HOW TO SET THE DIVIDING RATIO OF THE

PROGRAMMABLE DIVIDER

(1) Transfer of the 18th bit data (CONT terminal is "L" )

Total divider N is given by the following formulas in addition to the

prescaler used in the previous stage.

N=8 • (32M+S) M : 9 bit main counter divider

S : 5 bit swallow counter divider

The M and S counters are binary the possible ranges of divider are

as follows.

32≤M≤511

0≤S≤31

Therefore, the range of divider N is 8,192 to 131,064.

The tuning frequency fVCO is given in the following equations.

fVCO=fREF×N

=7.8125×8×(32M+S)

=62.5×(32M+S) [kHz]

Therefore, the tuning frequency range is 64MHz to 1023.9375MHz.

(2) Transfer of the 19th bit data (CONT terminal is "L" )

Total divider N is given by the following formulas in addition to the

prescaler used in the previous stage.

N=8 • (32M+S) M : 10 bit main counter divider

S : 5 bit swallow counter divider

The M and S counters are binary the possible ranges of divider are

as follows.

32≤M≤1023

0≤S≤31

Therefore, the range of divider N is 8,192 to 262,136.

The tuning frequency fVCO is given in the following equations.

fVCO=fREF×N

=3.90625×8×(32M+S)

=31.25×(32M+S) [kHz]

Therefore, the tuning frequency range is 32MHz to 1023.96875

MHz.

(3) Transfer of the 19th bit data (CONT terminal is "open")

Total divider N is given by the following formulas in addition to the

prescaler used in the previous stage.

N=8 • (32M+S) M : 10 bit main counter divider

S : 5 bit swallow counter divider

The M and S counters are binary the possible ranges of divider are

as follows.

32≤M≤1023

0≤S≤31

Therefore, the range of divider N is 8,192 to 262,136.

The tuning frequency fVCO is given in the following equations.

fVCO=fREF×N

=6.25×8×(32M+S)

=50.0×(32M+S) [kHz]

But, the tuning frequency range is 51.2MHz to 1300MHz from the

maxmum prescaler operating frequency.

TEST MODE DATA SET UP METHOD

The data for the test mode uses 20 to 27bits. Data is latched when

the 27th clock signal falls.

(1) When transferring 3-wire 27 bit data

ENA

CLK

1

BAND SW

DATA

M COUNTER DIVIDER

RATIO SETTING

(2) Test Mode Bit Set Up

X

:Random, 0 or 1.normal "0"

T0, T1,&T2 :Set up test modes

RSa, Rsa :Set the frequency divider of the reference

frequency

OS

:Set up the tuning amplifier

19 20

27

S COUNTER DIVIDER X X T2 T1 T0 RSa RSb 0S

RATIO SETTING

TEST DATA SETTING

READ INTO LATCH

6

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