MA82380 데이터 시트보기 (PDF) - Intel

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MA82380

HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS

Intel 

M82380

Enhancements are added to the M82380 for cas-

cading external interrupt controllers Master to Slave

handshaking takes place on the data bus instead of

dedicated cascade lines

1 1 4 WAIT STATE GENERATOR

The Wait State Generator is a programmable

READY generation circuit for the i386 processor

bus A peripheral requiring wait states can request

the Wait State Generator to hold the processor’s

READY input inactive for a predetermined number of

bus states Six different wait state counts can be

programmed into the Wait State Generator by soft-

ware three for memory accesses and three for I O

accesses A block diagram of the M82380 Wait

State Generator is shown in Figure 5

The peripheral being accessed selects the required

wait state count by placing a code on a 2-bit wait

state select bus This code along with the M IO sig-

nal from the bus master is used to select one of six

internal 4-bit wait state registers which has been

programmed with the desired number of wait states

From zero to fifteen wait states can be programmed

into the wait state registers The Wait State Genera-

tor tracks the state of the processor or current bus

master at all times regardless of which device is the

current bus master and regardless of whether or not

the Wait State Generator is currently active

The M82380 Wait State Generator is disabled by

making the select inputs both high This allows hard-

ware which is intelligent enough to generate its own

ready signal to be accessed without penalty As pre-

viously mentioned deselecting the Wait State Gen-

erator does not disable its ability to determine the

proper number of wait states due to pipeline status

in subsequent bus cycles

The number of wait states inserted into a pipelined

bus cycle is the value in the selected wait state reg-

ister If the bus master is operating in the non-pipe-

lined mode the Wait State Generator will increase

the number of wait states inserted into the bus cycle

by one

On reset the Wait State Generator’s registers are

loaded with the value FFH giving the maximum

number of wait states for any access in which the

wait state select inputs are active

1 1 5 DRAM REFRESH CONTROLLER

The M82380 DRAM Refresh Controller consists of a

24-bit refresh address counter and bus arbitration

logic The output of Timer 1 is used to periodically

request a refresh cycle When the controller re-

ceives the request it requests access to the system

bus through the HOLD signal When bus control is

acknowledged by the processor or current bus mas-

ter the refresh controller executes a memory read

operation at the address currently in the Refresh Ad-

dress Register At the same time it activates a re-

fresh signal (REF) that the memory uses to force a

refresh instead of a normal read Control of the bus

is transferred to the processor at the completion of

this cycle Typically a refresh cycle will take six clock

cycles to execute on an i386 processor bus

Figure 5 M82380 Wait State Generator Block Diagram

271070 – 6

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