MA82380 데이터 시트보기 (PDF) - Intel
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MA82380 Datasheet PDF : 134 Pages
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M82380
M82380
HIGH PERFORMANCE 32-BIT DMA CONTROLLER
WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS
CONTENTS
PAGE
1 0 FUNCTIONAL OVERVIEW
6
1 1 M82380 Architecture
6
1 1 1 DMA Controller
7
1 1 2 Programmable Interval Timers
8
1 1 3 Interrupt Controller
9
1 1 4 Wait State Generator
10
1 1 5 DRAM Refresh Controller
10
1 1 6 CPU Reset Function
11
1 1 7 Register Map Relocation
11
1 2 Host Interface
11
2 0 i386TM PROCESSOR HOST INTERFACE
12
2 1 Master and Slave Modes
13
2 2 M80386 Interface Signals
13
2 2 1 Clock (CLK2)
13
2 2 2 Data Bus (D0 – D31)
13
2 2 3 Address Bus (A31 – A2)
14
2 2 4 Byte Enable (BE3– BE0)
14
2 2 5 Bus Cycle Definition Signals (D C W R M IO)
15
2 2 6 Address Status (ADS)
15
2 2 7 Transfer Acknowledge (READY)
15
2 2 8 Next Address Request (NA)
15
2 2 9 Reset (RESET CPURST)
15
2 2 10 Interrupt Out (INT)
17
2 3 M82380 Bus Timing
17
2 3 1 Address Pipelining
17
2 3 2 Master Mode Bus Timing
17
2 3 3 Slave Mode Bus Timing
20
3 0 DMA CONTROLLER
21
3 1 Functional Description
22
3 2 Interface Signals
23
3 2 1 DREQn and EDACK (0 – 2)
24
3 2 2 HOLD and HLDA
24
3 2 3 EOP
24
3 3 Modes of Operation
24
3 3 1 Target Requester Definition
25
3 3 2 Buffer Transfer Processes
25
3 3 3 Data Transfer Modes
26
3 3 4 Channel Priority Arbitration
30
3 3 5 Combining Priority Modes
32
3 3 6 Bus Operation
33
3 4 Bus Arbitration and Handshaking
34
3 4 1 Synchronous and Asynchronous Sampling of DREQn and EOP
37
3 4 2 Arbitration of Cascaded Master Requests
39
3 4 3 Arbitration of Refresh Requests
41
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