MA82380 데이터 시트보기 (PDF) - Intel
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MA82380 Datasheet PDF : 134 Pages
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M82380
CONTENTS
5 0 PROGRAMMABLE INTERVAL TIMER
5 1 Functional Description
5 1 1 Internal Architecture
5 2 Interface Signals
5 2 1 CLKIN
5 2 2 TOUT1 TOUT2 TOUT3
5 2 3 GATE
5 3 Modes of Operation
5 3 1 Mode 0 Interrupt on Terminal Count
5 3 2 Mode 1 Gate Retriggerable One-Shot
5 3 3 Mode 2 Rate Generator
5 3 4 Mode 3 Square Wave Generator
5 3 5 Mode 4 Initial Count Triggered Strobe
5 3 6 Mode 5 Gate Retriggerable Strobe
5 3 7 Operation Common to All Modes
5 4 Register Set Overview
5 4 1 Counter 0 1 2 3 Registers
5 4 2 Control Word Register I II
5 5 Programming
5 5 1 Initialization
5 5 2 Read Operation
5 6 Register Bit Definitions
6 0 WAIT STATE GENERATOR
6 1 Functional Description
6 2 Interface Signals
6 2 1 READY
6 2 2 READYO
6 2 3 WSC(0 – 1)
6 3 Bus Function
6 3 1 Wait States in Non-Pipelined Cycle
6 3 2 Wait States in Pipelined Cycle
6 3 3 Extending and Early Terminating Bus Cycle
6 4 Register Set Overview
6 5 Programming
6 6 Register Bit Definition
6 7 Application Issues
6 7 1 External ‘READY’ Control Logic
7 0 DRAM REFRESH CONTROLLER
7 1 Functional Description
7 2 Interface Signals
7 2 1 TOUT1 REF
7 3 Bus Function
7 3 1 Arbitration
7 4 Modes of Operation
7 4 1 Word Size and Refresh Address Counter
7 5 Register Set Overview
7 6 Programming
7 7 Register Bit Definition
4
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