MA82380 데이터 시트보기 (PDF) - Intel

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MA82380

HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS

Intel 

M82380

The M82380 DMA controller transfers blocks of data

(buffers) in three modes Single Buffer Buffer Auto-

Initialize and Buffer Chaining In the Single Buffer

Process the M82380 DMA Controller is pro-

grammed to transfer one particular block of data

Successive transfers then require reprogramming of

the DMA channel Single Buffer transfers are useful

in systems where it is known at the time the transfer

begins what quantity of data is to be transferred and

there is a contiguous block of data area available

The Buffer Auto-Initialize Process allows the same

data area to be used for successive DMA transfers

without having to reprogram the channel

The Buffer Chaining Process allows a program to

specify a list of buffer transfers to be executed The

M82380 DMA Controller through interrupt routines

is reprogrammed from the list The channel is repro-

grammed for a new buffer before the current buffer

transfer is complete This pipelining of the channel

programming process allows the system to allocate

non-contiguous blocks of data storage space and

transfer all of the data with one DMA process The

buffers that make up the chain do not have to be in

contiguous locations

Channel priority can be fixed or rotating Fixed priori-

ty allows the programmer to define the priority of

DMA channels based on hardware or other fixed pa-

rameters Rotating priority is used to provide periph-

erals access to the bus on a shared basis

With fixed priority the programmer can set any

channel to have the current lowest priority This al-

lows the user to reset or manually rotate the priority

schedule without reprogramming the command reg-

isters

1 1 2 PROGRAMMABLE INTERVAL TIMERS

Four 16-bit programmable interval timers reside

within the M82380 These timers are identical in

function to the timers in the M82C54 Programmable

Interval Timer All four of the timers share a common

clock input which can be independent of the system

clock The timers are capable of operating in six dif-

ferent modes In all of the modes the current count

can be latched and read by the i386 processor at

any time making these very versatile event timers

Figure 3 shows the functional components of the

Programmable Interval Timers

The outputs of the timers are directed to key system

functions making system design simpler Timer 0 is

routed directly to an interrupt input and is not avail-

able externally This timer would typically be used to

generate time-keeping interrupts

Timers 1 and 2 have outputs which are available for

general timer counter purposes as well as special

functions Timer 1 is routed to the refresh control

logic to provide refresh timing Timer 2 is connected

to an interrupt request input to provide other timer

functions Timer 3 is a general purpose timer coun-

ter whose output is available to external hardware It

is also connected internally to the interrupt request

which defaults to the highest priority (IRQ0)

Figure 3 Programmable Interval Timers Block Diagram

271070 – 4

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