MAX4800A 데이터 시트보기 (PDF) - Maxim Integrated
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MAX4800A
Maxim Integrated
MAX4800A Datasheet PDF : 16 Pages
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MAX4800A/MAX4802A
Low-Charge-Injection, 8-Channel, High-Voltage
Analog Switches with 20MHz Serial Interface
Electrical Characteristics (continued)
(VDD = +2.7V to +6V, VPP = +40V to (VNN + 200V), VNN = -40V to -160V, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
VNN Supply Dynamic Current
ANALOG SWITCH
50kHz
VPP = +40V,
VNN = -160V
TA = 0°C
TA = +25°C
TA = +70°C
INN
output
switching
frequency
with no load
VPP = +100V,
VNN = -100V
VPP = +160V,
VNN = -40V
TA = 0°C
TA = +25°C
TA = +70°C
TA = 0°C
TA = +25°C
TA = +70°C
6.5
6.5
6.5
4.0
4.0
mA
4.0
4.0
4.0
4.0
Turn-On Time
tON
VNO_ = VPP - 10V, RL = 10kΩ, VNN = -40V
to -160V
5
μs
Turn-Off Time
tOFF
VNO_ = VPP - 10V, RL = 10kΩ, VNN = -40V
to -160V
5
μs
Output Switching Frequency
Maximum VCOM_,
VNO_ Slew Rate
LOGIC TIMING (Figure 1)
fSW
dV/dt
Duty cycle = 50%
(Note 3)
50
kHz
20
V/ns
CLK Frequency
DIN to CLK Setup Time
fCLK
Daisy chaining
VDD = +5V ±10%
VDD = +3V ±10%
tDS
VDD = +5V ±10%
VDD = +3V ±10%
10
16
20
MHz
10
ns
DIN to CLK Hold Time
tDH
VDD = +5V ±10%
VDD = +3V ±10%
3
ns
3
CLK to LE Setup Time
tCS
VDD = +5V ±10%
VDD = +3V ±10%
36
ns
65
LE Low Pulse Width
CLR High Pulse Width
CLK Rise and Fall Times
(Note 3)
tWL
tWC
tR, tF
VDD = +5V ±10%
VDD = +3V ±10%
VDD = +5V ±10%
VDD = +3V ±10%
VDD = +5V ±10%
VDD = +3V ±10%
14
ns
22
20
ns
40
50
ns
50
CLK to DOUT Delay
tDO
VDD = +5V ±10%, CL ≤ 20pF
VDD = +3V ±10%, CL ≤ 20pF
6
42
ns
12
80
Note 1: Specifications at 0°C are guaranteed by correlation and design.
Note 2: The analog-signal input VCOM_ and VNO_ must satisfy VNN ≤ (VCOM_, VNO_) ≤ VPP, or remain unconnected during
power-up and power-down.
Note 3: Guaranteed by design and characterization; not production tested.
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