MB89673 데이터 시트보기 (PDF) - Fujitsu
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MB89673 Datasheet PDF : 59 Pages
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MB89670/A Series
s PRODUCT LINEUP
Part number
Parameter
Classification
ROM size
RAM size
CPU functions
Ports
Option
21-bit time-
base timer
8/16-bit up/
down counter
16-bit timer/
counter
8/16-bit timer
counter
8-bit PWM
timer 1,
8-bit PWM
timer 2
8-bit PWM
timer 3,
8-bit PWM
timer 4, 5, 6
8-bit serial I/O
MB89673*1
MB89677A
MB89P677A
MB89PV670A
Mass production products
(mask ROM products)
One-time PROM product Piggyback/ evaluation
(for development)
product (for development)
8 K × 8 bits
32 K × 8 bits
(internal mask ROM) (internal mask ROM)
32 K × 8 bits
(internal PROM)
48 K × 8 bits
(external ROM)
384 × 8 bits
1 K × 8 bits
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.4 µs/10 MHz to 6.4 µs/10 MHz
3.6 µs/10 MHz to 57.6 µs/10 MHz
Output ports (N-channel open-drain):
Output ports (CMOS):
I/O ports (N-channels open-drain):
I/O ports (CMOS):
Input ports:
Total:
14 (12 also serve as peripherals.)
8 (All also serve as peripherals.)
7 (All also serve as peripherals.)
32 (All also serve as peripherals.)
8 (All also serve as peripherals.)
69
Specify when ordering masking
Set with EPROM
programmer
Setting not possible
21 bits (0.81 ms, 3.27 ms, 26.21 ms, 419 ms/10 MHz)
8 bits × 2 channels or 16 bits × 1 channel
Timer operation
Up/down counter operation
Phase difference counting (successive double mode, quadruple mode)
16-bit timer operation
16-bit event counter operation (edge selectability)
8 bits × 2 channels or 16 bits × 1 channel
Reload timer operation (toggled output capable)
Event counter operation
8 bits × 2 channels reload timer operation (toggled output capable)
8 bits × 2 channels PWM operation (four fixed frequency)
8 bits × 1 channel PPG operation (variable frequency)
Capable of output switching between 2 channels
8-bit reload timer operation (toggled output capable)
8-bit PWM operation (four fixed frequency)
Capable of output switching between 2 channels
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks)
(Continued)
3
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