MC100LVEL31DR2 데이터 시트보기 (PDF) - ON Semiconductor
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MC100LVEL31DR2 Datasheet PDF : 8 Pages
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MC100LVEL31
S1
D2
CLK 3
R4
S
D
Flip Flop
R
8 VCC
7Q
6Q
5 VEE
Figure 1. Logic Diagram and Pinout Assignment
Table 1. PIN DESCRIPTION
PIN
FUNCTION
Table 2. TRUTH TABLE
D S R CLK Q
Q
CLK
Q, Q
D
R
S
VCC
VEE
EP
ECL Clock Input
ECL Differential Data Outputs
ECL Data Input
ECL Reset Input
ECL Set Input
Positive Supply
Negative Supply
Exposed pad must be connected to a sufficient
thermal conduit. Electrically connect to the
most negative supply or leave floating open.
LLL
HL L
XHL
XLH
XHH
Z
L
H
Z
H
L
X
H
L
X
L
H
X Undef Undef
Z = LOW to HIGH Transition
X = Don’t Care
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE
NECL Mode Power Supply
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
Iout
Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI VCC
VI VEE
8 to 0
V
−8 to 0
V
6 to 0
V
−6 to 0
V
50
mA
100
mA
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 SOIC
8 SOIC
−40 to +85
−65 to +150
190
130
°C
°C
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 SOIC
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
41 to 44 ± 5%
185
140
°C/W
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 TSSOP
qJA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
41 to 44 ± 5%
129
84
°C/W
°C/W
°C/W
Tsol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
°C
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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