SAA7131E 데이터 시트보기 (PDF) - NXP Semiconductors.
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SAA7131E
NXP Semiconductors.
SAA7131E Datasheet PDF : 66 Pages
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NXP Semiconductors
SAA7131E
Global standard low-IF and PCI audio and video decoder
Table 4. Power supply pins
Symbol Pin
VSSA1
VDDA1
A2 and A5
B3, D3, F4 and F5
Type[1]
AG
AS
VSSA2 B1, B2, E1, E2, F1, H1 and H2
AG
VDDA2 C2, D2, F3, G3, H3 and J3
AS
VSSA3
VDDA3
VSSD1
VDDD1
D7, D12, E7, E12, F7, F12, H5, H8, J5, AG
J8, K3 to K6, K8, L1 to L6, L8, M3 to M6,
N3, P1 to P3, R3, T2 and T3
F8 to F11, G7, G8, H7, J6, J7, K7, L7 AS
and M7
C5, C6, D4 and E3 to E5
VG
C4 and E6
VS
VSSD2 D5 and D6
VG
VDDD2 B4, B5 and C3
VS
VSSD3
VDDD3
H9 to H13, H16, J9 to J13, K9 to K13, VG
K16, L9 to L13 and M8 to M13
G9 to G13, H14, H15, J14, K14, K15 and VS
N7 to N13
Description
analog ground 1, for integrated analog signal processing
analog supply voltage 1 (1.8 V), for integrated analog signal
processing of IF demodulator part
analog ground 2, for integrated analog signal processing
analog supply voltage 2 (3.3 V), for integrated analog signal
processing of IF demodulator part
analog ground 3, for integrated analog signal processing
analog supply voltage 3 (3.3 V), for integrated analog signal
processing of audio-video decoder part
digital ground 1, for digital circuit, core and I/Os
digital supply voltage 1 (1.8 V), for digital circuits, core and
I/Os of IF demodulator part
digital ground 2, for digital circuits, core and I/Os
digital supply voltage 2 (3.3 V), for digital circuits, core and
I/Os of IF demodulator part
digital ground 3, for digital circuit, core and I/Os
digital supply voltage 3 (3.3 V), for digital circuits, core and
I/Os of audio and video decoder part
[1] The pin types are defined in Table 13.
Table 5. JTAG test interface pins (for boundary scan test)
Symbol
Pin
Type[1]
Description
Audio and video decoder
TDID
C7
I
test serial data input: tie HIGH or let float for normal operation
TDOD
C8
O
test serial data output: 3-state
TMSD
C9
I
test mode select input: tie HIGH or let float for normal operation
TCKD
C10
I
test clock input: drive LOW for normal operation
TRSTD_N
C11
I
test reset input: drive LOW for normal operation
IF demodulator
TDII
B6
I
test serial data input: tie HIGH or let float for normal operation
TDOI
B7
O
test serial data output: 3-state
TMSI
B8
I
test mode select input: tie HIGH or let float for normal operation
TCKI
B9
I
test clock input: drive LOW for normal operation
TRSTI_N
B10
I
test reset input: drive LOW for normal operation
[1] The pin types are defined in Table 13.
SAA7131E_3
Product data sheet
Rev. 03 — 19 May 2008
© NXP B.V. 2008. All rights reserved.
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