TA8430AF
FUNCTION
INPUT
OUTPUT
ST
EN
PS
IN
φ
φ
UPPER SIDE SATURATION VOLTAGE
H
H
L
L
L
H
VS − VCE (SAT) U
H
H
L
H
H
L
VS−VCE (SAT) U
H
H
H
L
L
H
VREG (Note)
H
H
H
H
H
L
VREG (Note)
Note: VREG is a voltage appeared at PIN (7) and its value becomes approximately equal to VOUT in power
operation period.
ST
ENA
ENB
H
L
H
H
H
L
H
H
H
L
X
X
X:
Don’t Care
∞:
High Impedance
φA, φA
∞
ENABLE
ENABLE
∞
φB, φB
ENABLE
∞
ENABLE
∞
MODE
OPERATION
OPERATION
OPERATION
STAND−BY
INPUT STEP CIRCUIT DIAGRAM
VREG OUTPUT CIRCUIT DIAGRAM
VREG output voltage can be selected with RREG exterior
resistance.
If VREG is not used (as in the case of double−phase
magnetization), use pin (7) in the open position.
(Do not connect to VCC or GND pins.)
Use the following formula to obtain the output voltage.
VOUT ≈ VREG ≈ RREG × 56 × 10−6
3
2003-08-04