SK70704PE 데이터 시트보기 (PDF) - Intel
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SK70704PE Datasheet PDF : 54 Pages
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1168 Kbps HSDL Data Pump Chip Set — SK70704/SK70707 or SK70708
Table 2. SK70707/SK70708 HDX Pin Assignments/Signal Descriptions
Group
707
708
Pin # Pin #
Symbol
I/O
Description
14
10
RFST
Receive Frame and Stuff Bit Indicator. Goes High for 18 consecutive
O ICLK periods to indicate four stuffing bits
(b7007 - 7010) and 14 frame bits (b1-14) on RDATA.
I1 18.688 MHz HDSL Reference Clock. In LTU Mode, this clock generates
17
13
REFCLK
transmit and receive timing and must have ±32 ppm accuracy. In NTU
O Mode, this output is derived by dividing CK37M by two.
Operation Mode Select. When LTU is High, the Data Pump operates in
20
16
LTU
I LTU mode; when LTU is Low, the Data Pump operates in NTU mode.
Tied to internal pull-up device.
21
17
ICLK
O
Bit Rate Clock. Nominally 1168 kHz, REFCLK is the source of ICLK in
LTU Mode. CK37M is the source of ICLK in NTU Mode.
Loss of Sync Word Indicator. Normally Low in Active States, goes
49
30
LOSW
O High to indicate receipt of six consecutive mismatched frame synch
words. LOSW is logic High in all states except Active States.
User Port
8
Receive HDSL Data Stream. Output data to HDSL framer at 1168 kbps:
HDSL payload of Loop 1 or Loop 2 bytes plus the Z-bits,
8
RDATA
O
eoc, crc, losd, febe, ps, bpv, hrp, indc/indr and uib bits,
Sync bits for frame positions b1-14,
Stuff bits for frame positions b7007 - 7010.
RDATA bits are forced high in all states except the Active State.
9
7
RFP
Receive Frame Pulse. Low for one ICLK cycle during the last bit of the
O
current HDSL receive frame on RDATA, either b7006 or b7010. Period
is within one baud time of 6 ms.2 RFP is valid when LOSW transitions
Low.
Transmit HDSL Data Stream. Input data from HDSL framer at
1168 kbps:
HDSL payload of Loop 1 or Loop 2 bytes plus the Z-bits,
eoc, crc, losd, febe, ps, bpv, hrp, indc/indr and uib bits,
15
11
TDATA
I1 Sync bits for frame positions b1-14,
Stuff dummy bits; may be 1s or 0s.
Tied to internal pull-up device.
When ACTIVE, the Data Pump is transparent and the HDSL framer must
generate the appropriate bits on TDATA as shown in Table 5.
User Port
16
12
Transmit Frame Pulse. Must be Low for one ICLK cycle during the last
bit of the current HDSL frame on TDATA, either b7006 or b7010. Period
TFP
I1 is within one baud time of 6 ms.2 If TFP is pulled Low and is Low again
three ICLK cycles later, RDATA, RFP, RFST, ICLK, CK9MEN and LOSW
go to tri-state. Tied to internal pull-up device.
1. This input is a Schmidt Triggered circuit and includes an internal pull-up device.
2. The period is 6 ms ±1/584 ms.
3. This input is a Schmidt Triggered circuit and includes an internal pull-down device.
Datasheet
11
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