M34D64-W 데이터 시트보기 (PDF) - STMicroelectronics

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M34D64-W

64 Kbit serial I²C bus EEPROM with hardware write control on top quarter of memory

STMicroelectronics 

Description

1

Description

M34D64-W

The M34D64-W are I2C-compatible electrically erasable programmable memory (EEPROM)

devices organized as 8192 x 8 bits.

These devices are compatible with the I2C memory protocol. This is a two-wire serial

interface that uses a bidirectional databus and serial clock. The devices carry a built-in 4-bit

Device Type Identifier code (1010) in accordance with the I2C bus definition.

The device behaves as a slave in the I2C protocol, with all memory operations synchronized

by the serial clock. Read and Write operations are initiated by a Start condition, generated

by the bus master. The Start condition is followed by a Device Select Code and Read/Write

bit (RW) (as described in Table 2.: Device select code), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit

time, following the bus master’s 8-bit transmission. When data is read by the bus master, the

bus master acknowledges the receipt of the data byte in the same way. Data transfers are

terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Figure 1. Logic diagram

VCC

3

E0-E2

SCL

WC

M34D64-W

SDA

VSS

Table 1. Signal names

Signal name

Function

E0, E1, E2

SDA

SCL

WC

VCC

VSS

Chip Enable

Serial Data

Serial Clock

Write Control

Supply voltage

Ground

AI02850c

Input

I/O

Input

Input

Direction

6/27

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