CDB4361
Figure 40.System Block Diagram and Signal Flow ................................................................................... 16
Figure 41.CS4361 ..................................................................................................................................... 17
Figure 42.CS8416 S/PDIF Input and Clock Control .................................................................................. 18
Figure 43.PCM Input Header and MUX .................................................................................................... 19
Figure 44.Passive Outputs ........................................................................................................................ 20
Figure 45.Mute Circuitry ............................................................................................................................ 21
Figure 46.Power Supply Connections ....................................................................................................... 22
Figure 47.Silkscreen Top .......................................................................................................................... 23
Figure 48.Top Side .................................................................................................................................... 24
Figure 49.Bottom Side .............................................................................................................................. 25
DS672DB2
3