HCF4029B 데이터 시트보기 (PDF) - STMicroelectronics

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HCF4029B

PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE

STMicroelectronics 

HCF4029B

PRESETTABLE UP/DOWN COUNTER

BINARY OR BCD DECADE

s MEDIUM SPEED OPERATION : 8MHz (Typ.)

at CL = 50pF and VDD - VSS = 10V

s MULTI-PACKAGE PARALLEL CLOCKING

FOR SYNCHRONOUS HIGH SPEED

OUTPUT RESPONSE OR RIPPLE

CLOCKING FOR SLOW CLOCK INPUT RISE

AND FALL TIMES

s "PRESET ENABLE" AND INDIVIDUAL "JAM"

INPUTS PROVIDED

s BINARY OR DECADE UP/DOWN

COUNTING

s BCD OUTPUTS IN DECADE MODE

s QUIESCENT CURRENT SPECIF. UP TO 20V

s STANDARDIZED SYMMETRICAL OUTPUT

CHARACTERISTICS

s INPUT LEAKAGE CURRENT

II = 100nA (MAX) AT VDD = 18V TA = 25°C

s 100% TESTED FOR QUIESCENT CURRENT

s MEETS ALL REQUIREMENTS OF JEDEC

JESD13B "STANDARD SPECIFICATIONS

FOR DESCRIPTION OF B SERIES CMOS

DEVICES"

DESCRIPTION

HCF4029B is a monolithic integrated circuit

fabricated in Metal Oxide Semiconductor

technology available in DIP and SOP packages.

HCF4029B consists of a four stage binary or

BCD-decade up/down counter with provisions for

look ahead carry in both counting modes. The

PIN CONNECTION

DIP

SOP

ORDER CODES

PACKAGE

TUBE

DIP

SOP

HCF4029BEY

HCF4029BM1

T&R

HCF4029M013TR

inputs consist of a single CLOCK, CARRY IN

(CLOCK ENABLE), BINARY/DECADE, UP/

DOWN, PRESET ENABLE, and four individual

JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT

signal are provided as outputs. A high PRESET

ENABLE signal allows information on the JAM

INPUTS to preset the counter to any state

asynchronously with the clock. A low on each JAM

line, when the PRESET-ENABLE signal is high,

resets the counter to its zero count. The counter

advances one count at the positive transition of

the clock when the CARRY-IN and PRESET

ENABLE signals are low. Advancement is

inhibited when the CARRY-IN or PRESET

ENABLE signals are high. The CARRY-OUT

September 2002

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