HI-7159A 데이터 시트보기 (PDF) - Renesas Electronics
부품명
상세내역
제조사
HI-7159A Datasheet PDF : 14 Pages
| |||
HI-7159A
Theory of Operation
The HI-7159A attains its 51/2 digit resolution through the use of
multiple integrations per conversion, creating an effective
integrator swing greater than the supply rails, and a successive
integration technique used to measure the residue on the
integrator capacitor to 51/2 digit accuracy.
In the 51/2 digit mode, the input voltage is integrated and
reference de-integrated four times. This results in a count with the
same effective resolution as a single integration with four times
the integrator swing amplitude. In this manner effective integrator
swings of 12V or greater can be achieved with 5V supplies.
The four integrations are spaced so that common-mode signals
whose frequency is an integer multiple of fCRYSTAL/40,000 are
rejected. In the 41/2 digit mode, only one input integration is
performed, thus the minimum frequency for common-mode
rejection becomes fCRYSTAL/10,000.
These first four integrations measure the input voltage to an
resolution of 31/2 digits, or 1mV/count. To achieve 51/2 digit
accuracy (10V/count), the error voltage remaining on the
integrator capacitor (representing the overshoot of the
integrator due to comparator delay and clock quantization)
must be measured and subtracted from the 31/2 digit result.
This is accomplished by multiplying the residue by a factor of
10, then integrating and reference de-integrating the error. This
error is subtracted from the 31/2 digit result, yielding a 41/2 digit
accurate result. The error remaining from this step is then
multiplied by 10 and subtracted, and the process is repeated a
third time to achieve an internal accuracy of 61/2 digits. This
result is rounded to 51/2 digits and transferred to the holding
register, where it can be accessed by the user through one of
the three communications modes.
Conversion Types
The HI-7159A offers the user a choice of three different
conversion types. They are: (1) the converter’s internal offset
voltage, measured by internally connecting VIN HI and VIN LO to
AGND and doing a conversion (Error Only Mode); (2) the input
voltage (VIN HI minus VIN LO) including the converter’s internal
offset (Uncompensated Mode); and (3) the input voltage including
internal offset errors, minus the internal offset errors
(Compensated Mode). This last measurement is a digital
subtraction of an Error Only conversion from an Uncompensated
conversion, and is the default conversion type. Since a
Compensated conversion consists of two conversions, it takes
twice as long to perform as the first two types.
Under some conditions, it may be desirable to increase the
conversion rate without loss of resolution or accuracy. Since
the short term drift of the internal offset error is slight when
temperature is controlled, it is not always necessary to convert
the error voltage once for every input voltage conversion. It is
possible for the host processor to do an error conversion
periodically, store the result, and subtract the error from a
stream of uncompensated input conversions with its own
internal ALU. In this way the conversion rate can be effectively
doubled.
FN2936 Rev 4.00
January 1999
Communication Modes
The HI-7159A A/D converter receives instructions from and
transmits data to the user host processor through one of four
communication modes. The modes are: parallel microprocessor
(Parallel); synchronous serial (Serial Mode 0); serial non-
addressed (Serial Mode 1); and serial addressed (Serial Mode
2). The mode is determined by the states of the SEL, SMS0, and
SMS1 pins as shown in Table 1.
The parallel mode allows the converter to be attached directly to
a microprocessor data bus. Data is read and written to the
device under control of the microprocessor’s RD, WR and CS
signals. Serial Mode 0 permits high speed serial data transfer at
up to 1 megabits/s. Serial Mode 1 reads and writes industry
standard serial data packets consisting of 1 start bit, 8 data bits,
1 parity bit (EVEN), and 1 stop bit, at one of 4 hardware
selectable baud rates. Serial Mode 2 is identical to Serial Mode
1 with the addition of addressing capabilities which allow up to
32 HI-7159As to share the same serial line, with each assigned
a unique address.
TABLE 1. COMMUNICATION MODE SELECTION
SEL PIN SM S0
COMMUNICATION MODE
28
PIN 18
SM S1
PIN 19
Parallel
Serial 0
Serial 1
Serial 2
VCC
DGND
DGND
DGND
N/A
DGND
DGND
VCC
N/A
DGND
VCC
DGND
All four modes follow the same interface protocol: a request or
a command is sent from the host to the HI-7159A, and the
converter responds with the requested data and, in the case of
a command, begins a new conversion.
Parallel Mode Operation
The parallel communication mode (Figure 3) is selected when
SEL (Pin 28) is high. Pins 18-25 become the eight bidirectional
data bits, P0-P7. Pins 15, 16, and 17 respectively become read
(RD), write (WR), and chip select (CS). Timing parameters for
the parallel mode are shown in Figure 1.
Serial Mode 0
Serial Mode 0 is the high speed synchronous serial interface,
directly compatible with the MCS-51 series of microcontrollers. It
is enabled by tying SEL (Pin 28), SMS0 (Pin 18) and SMS1 (Pin
19) low (Figure 4A). Pin 16 is the bidirectional serial data path,
and pin 15 is the data clock input. Data sent to the HI-7159A is
latched on the rising edge of the serial clock. See Figure 2A for
detailed timing information.
Only 8 data bits are used in this mode - no start, stop, or parity
bits are transmitted or received. CS must either be tied to
DGND or pulled low to access the device. The SAD0 - SAD3
and BRS0 - BRS1 pins are unused in this mode and should be
tied high.
Page 6 of 14
Share Link: 