SK100LVE111EPJ(2003) 데이터 시트보기 (PDF) - Semtech Corporation

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SK100LVE111EPJ
(Rev.:2003)

1:9 Differential LVECL/LVPECL Clock Driver with w/Enable Input

Semtech Corporation 

TEST AND MEASUREMENT PRODUCTS

AC Characteristics

SK100LVE111E

1 . 100LVE111E circuits are designed to meet the DC specifications shown in the table where transverse

airflow greater than 500 lfpm is maintained.

2 . These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.

3 . The differential propagation delay is defined as the delay from the crossing points of the differential

input signals to the crossing point of the differential output signals.

4 . The single-ended propagation delay is defined as the delay from the 50% point of the input signal to

the 50% point of the output signal.

5 . The within-device skew is defined as the worst case difference between any two similar delay paths

within a single device.

6 . VPP(min) is defined as the minimum input differential voltage which will cause no increase in the

propagation delay. The VPP(min) is AC limited for the LVE111E as a differential input as low as 500

mV will still produce full ECL levels at the output.

7 . CMR range is referenced to the most positive side of the differential input signal. Normal operation is

obtained if the high level falls within the specified range and the peak-to-peak voltage lies between

VPP(min) and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.5V.

8. For part ordering description, see TMD Part Ordering Information Data Sheet.

Application Notes

AN1002 - Interfacing Between ECL / LVECL / PECL / LVPECL - to - TTL / LVTTL / CMOS / LVCMOS

AN1003 - Termination Techniques for ECL / LVECL / PECL / LVPECL Devices

AN1004 - Interfacing Between LVDS and ECL / LVECL / PECL / LVPECL

AN1005 - Using ECL / LVECL Devices as PECL / LVPECL

AN1006 - Designing with 10K and 100K ECL / PECL Devices

Revision 3 / January 29, 2003

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