CAT24C21WE-T3 데이터 시트보기 (PDF) - ON Semiconductor

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CAT24C21WE-T3

1 kb Dual Mode Serial EEPROM for VESA “Plug-and-Play”

ON Semiconductor 

CAT24C21

Bi−Directional Mode (DDC2)

The following defines the features of the I2C bus protocol

in bi−directional mode (Figure 5):

1. Data transfer may be initiated only when the bus is

not busy.

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is high

will be interpreted as a START or STOP condition.

When in the bi−directional mode, all inputs to the VCLK

pin are ignored, except when a logic high is required to

enable write capability.

START Condition

The START condition (Figure 7) precedes all commands

to the device, and is defined as a HIGH to LOW transition

of SDA when SCL is HIGH. The CAT24C21 monitors the

SDA and SCL lines and will not respond until this condition

is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

Device Addressing

The bus Master begins a transmission by sending a

START condition. The Master then sends the address of the

particular slave device it is requesting. The four most

significant bits of the 8−bit slave address are fixed as 1010

for the CAT24C21 (see Figure 9). The next three significant

bits are “don’t care”. The last bit of the slave address

specifies whether a Read or Write operation is to be

performed. When this bit is set to 1, a Read operation is

selected, and when set to 0, a Write operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT24C21 monitors the bus and responds

with an acknowledge (on the SDA line) when its address

matches the transmitted slave address. The CAT24C21 then

performs a Read or Write operation depending on the state

of the R/W bit.

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge (ACK). The

acknowledging device pulls down the SDA line during the

ninth clock cycle, signaling that it has received the 8 bits of

data (Figure 8).

The CAT24C21 responds with an ACK after receiving a

START condition and its slave address. If the device has

been selected along with a write operation, it responds with

an ACK after receiving each 8−bit byte.

When the CAT24C21 is in a READ mode it transmits 8

bits of data, releases the SDA line, and monitors the line for

an ACK. Once it receives this ACK, the CAT24C21 will

continue to transmit data. If no ACK is sent by the Master,

the device terminates data transmission and waits for a

STOP condition.

Write Operations

VCLK must be held high in order to program the device.

This applies to byte write and page write operation. Once the

device is in its self−timed program cycle, VCLK can go low

and not affect programming.

Byte Write

In the Byte Write mode (Figure 10), the Master device

sends the START condition and the slave address

information (with the R/W bit set to zero) to the Slave

device. After the Slave generates an ACK, the Master sends

the byte address that is to be written into the address pointer

of the CAT24C21. After receiving another ACK from the

Slave, the Master device transmits the data byte to be written

into the addressed memory location. The CAT24C21

acknowledges once more and the Master generates the

STOP condition, at which time the device begins its internal

programming cycle to nonvolatile memory (Figure 6).

While this internal cycle is in progress, the device will not

respond to any request from the Master device.

SCL

tSU:STA

SDA IN

SDA OUT

tF

tHIGH

tR

tLOW

tLOW

tHD:STA

tHD:DAT

tSU:DAT

tAA

tDH

Figure 5. Bus Timing

tSU:STO

tBUF

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