MAS9090B 데이터 시트보기 (PDF) - Micronas
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MAS9090B Datasheet PDF : 30 Pages
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TIMING SPECIFICATIONS
x Serial Control Port Timing
DA9090B.001
January 14, 1998
Parameter
Symbol Conditions
Min
Frequency of CCLK
fCCLK
Period of CCLK high
tWHC Measured from VIH to VIH 160
Period of CCLK low
tWLC Measured from VIL to VIL 160
Rise time of CCLK
tRC
Measured from VIL to VIH
Fall time of CCLK
tFC
Measured from VIH to VIL
Hold time, CCLK high to CS low
tHCHS
10
Setup time, CS low to CCLK high
tSSLCH
50
Setup time, valid CI data to CCLK high tSDCH
50
Hold time, CCLK high to invalid CI data tHCHD
50
Delay time, CCLK low to valid CO data tDCLD Load = 100 pF
Delay time, CS low to valid CO data
tDSD
Delay time, CS high or 8th CCLK low to tDSZ
10
CO high impedance
Hold time, 8th CCLK high to CS high
tH8CHS
100
Setup time, CS high to CCLK high
tSSHCH
100
Typ Max Unit
2.048 MHz
ns
ns
50
ns
50
ns
ns
ns
ns
ns
80
ns
50
ns
80
ns
ns
ns
x Serial Control Port Timing Diagram (MICROWIRE mode)
tWHC
tWLC
tHCHS
tRC
tFC
CCLK
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
tSSLCH
tHCHS
CS
BYTE 1
tSSHCH
BYTE 2
tHCHSH
tSDCH tHCHD
t t HCHSH SSLCH
CI
7
65
43
21 0
7
65
43
21 0
tDSD
tDCLD
tDSZ
CO
7
65
43
210
7
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