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MB89143 데이터 시트보기 (PDF) - Fujitsu

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MB89143 Datasheet PDF : 31 Pages
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MB89143A/144A
s PRODUCT LINEUP
Part number
Parameter
Classification
MB89143A
MB89144A
Mass production products
(mask ROM products)
MB89P147
One-time PROM
product
MB89PV140
Piggyback/evaluation product
(for evaluation and development)
ROM size
8 K × 8 bits
12 K × 12 bits
32 K × 8 bits
Internal PROM
32 K × 8 bits
External ROM
(Piggyback)
RAM size
256 × 8 bits
1 K × 8 bits
Internal
CPU functions
Number of instructions:
136
Instruction bit length:
8 bits
Instruction length:
1 to 3 bytes
Data bit length:
1, 8, 16 bits
Minimum execution time:
0.5 µs/8 MHz to 8.0 µs/8 MHz, 61 µs/32.768 kHz
Interrupt processing time:
4.5 µs/8 MHz to 72.0 µs/8 MHz, 562.5 µs/32.768 kHz
Note: The above times change according to the gear function.
Ports
High-voltage output ports (P-ch open-drain):
24 (P40 to P47, P50 to P57, and P60 to P67)
Buzzer output (P-ch open-drain, high-voltage):1
Output ports (CMOS):
4 (P20 to P23)
Input ports (CMOS):
2 (P70 and P71, function as X0A and X1A pins when
dual-clock system is used.)
I/O ports (CMOS):
23 (P00 to P07, P10 to P17, P30, and P32 to P37)
I/O port (N-channel open-drain): 1 (P31)
Total:
55
Time-base timer
Capable of generating four different intervals (at 8.0-MHz oscillation):
0.26 ms, 0.51 ms, 1.02 ms, and 0.524 s
8/16-bit timer
counter
8/16-bit timer operation (Operating clock, internal clock, external trigger)
8/16-bit event counter operation (Rising edge/falling edge/both edges selectability)
8-bit Serial I/O
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 4, 8, 16 system clock cycles)
A/D converter
8-bit resolution × 8 channels
A/D conversion mode (with
conversion time of 22 µs/8 MHz, and
highest gear speed)
Continuous activation by external
activation capable
10-bit resolution × 12 channels
A/D conversion mode (with conversion time of 16.5 µs/
8 MHz, and highest gear speed)
Sense mode (with conversion time of 9.0 µs/8 MHz,
and highest gear speed)
Continuous activation enabled by external activation
capable
External interrupt
2 independent channels (edge selection, interrupt vector, source flag)
Rising edge/falling edge/both edges selectability
Built-in analog noise canceller
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Buzzer output
1.95 or 3.91 kHz selectable (at 8-MHz oscillation)
Output to a high-voltage pin
(Continued)
3

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