NT7181FQ 데이터 시트보기 (PDF) - Novatek Microelectronics
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NT7181FQ Datasheet PDF : 15 Pages
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1 Features
! 28:4 Data Channel Compression at up to 297 Megabytes
per Second Throughput
! Suited for VGA, SVGA, XGA and Dual pixel SXGA,
UXGA Display Data Transmission From Controller to
Display With Very Low EMI
! 28 Data Channels and Clock-In Low-Voltage TTL and 4
Data Channels and Clock-Out Low-Voltage Differential
! Operates From a Single 3.3V Supply With 250mW (Typ)
! Low profile 56 Lead TSSOP Package
! Clock edge Programmable for Transmitter
! Wide Phase-Lock Input Frequency Range: 25 MHz To
85 MHz
! Supports Spread Spectrum Clock Generator
! Suggests to use for LCD monitor only
! No External Components Required for PLL
2 General Description
The NT7181 transmitter contains four 7-bit parallel-load serial-out registers, a 7x clock synthesizer, and five low-voltage
differential (LVDS) line in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL)
data to be synchronously transmitted over four balanced-pair conductors for receipt by a compatible receiver, such as the
DS90CF386 or THC63LVDF84A.The NT7181 transmitter is offered with programmable edge data strobes for convenient
interface with a variety of graphic controllers. The NT7181 transmitter can be programmed for rising edge strobe(RFB=1) or
falling edge strobe(RFB=0) through the RFB pin. When transmitting, data bits D0 - D27 are each loaded into registers of the
NT7181 on the rising edge or falling edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times
and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock
(TCLK) are then output to LVDS output drivers. The frequency of TCLK is the same as the input clock, CLKIN.
The NT7181 requires no external components and little or no control. The data bus appears the same at the input to the
transmitting and output of the receiver with the data transmission transparent to the user. The only user intervention is the
possible use of the shutdown/clear ( PWDN ) active-low input to inhibit the clock and shut off the LVDS output drivers for
lower power consumption. A low level on this signal clears all internal registers to a low level.
The NT7181 are characterized for operation over free-air temperature ranges of 0°C to 70°C.
2.1 Block Diagrams
CMOS / TTL INPUTS
7
TD0-6
7
TD7-13
7
TD14-20
7
TD21-27
(TRANSMIT CLOCK IN)
(25 MHz To 85 MHz)
POWER DOWN
NT7181
T
T
L
P
A
R
A
L
L
E
L
|
T
O
|
L
V
D
S
PLL
DATA (LVDS)
T0P
T0M
T1P
T1M
T2P
T2M
(175 Mbit/s To 595 Mbit/s On
Each LVDS
Cnannel)
T3P
T3M
TCLKP
TCLKM
CLOCK (LVDS)
(25 MHz To 85 MHz)
3
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