HIP4086A 데이터 시트보기 (PDF) - Renesas Electronics
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HIP4086A Datasheet PDF : 17 Pages
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HIP4086, HIP4086A
Pin Descriptions (Continued)
PIN NUMBER
10
SYMBOL
DIS
17
24
14
20
21
22
19
NOTE: x = A, B or C.
AHO
BHO
CHO
(xHO)
VDD
ALO
BLO
CLO
(xLO)
DESCRIPTION
Disable Input. Logic level input that when taken high sets all six outputs low. DIS high overrides
all other inputs. With DIS low, the outputs are controlled by the other inputs. DIS can be driven
by signal levels of 0V to 15V (no greater than VDD).
High-Side Outputs. Connect to the gates of the high-side power MOSFETs in each phase.
Positive Supply. Decouple this pin to VSS (Pin 6).
Low-Side Outputs. Connect the gates of the low-side power MOSFETs to these pins.
Ordering Information
PART NUMBER
(Note 3)
PART
MARKING
TEMP RANGE
(°C)
CHARGE
PUMP
PACKAGE
PKG.
DWG. #
HIP4086AB (Note 1)
HIP4086AB
-40 to +125
Yes
24 Ld SOIC
M24.3
HIP4086ABZ (Notes 1, 2) HIP4086ABZ
-40 to +125
Yes
24 Ld SOIC (RoHS Compliant) M24.3
HIP4086APZ (Note 2)
HIP4086APZ
-40 to +125
Yes
24 Ld PDIP (RoHS Compliant) E24.3
HIP4086AABZ (Notes 1, 2) HIP4086AABZ
-40 to +125
No
24 Ld SOIC (RoHS Compliant) M24.3
HIP4086DEMO1Z
HIP4086 Demonstration Board
NOTES:
1. Add “T”, suffix for 1k unit tape and reel option. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for HIP4086, HIP4086A. For more information on MSL, please see Technical
Brief TB363.
FN4220 Rev 1.00
January 12, 2017
Page 4 of 17
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