N386SX 데이터 시트보기 (PDF) - Intel

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N386SX

Intel387™ SX MATH COPROCESSOR

Intel 

Intel387TM SX MATH COPROCESSOR

2 0 FUNCTIONAL DESCRIPTION

The Intel387 SX Math CoProcessor is designed to

support the Intel386 SX Microprocessor and effec-

tively extend the CPU architecture by providing fast

execution of arithmetic instructions and transcen-

dental functions This component contains internal

power management circuitry for reduced active pow-

er dissipation and an automatic idle mode

2 1 Feature List

 New power saving design provides low power

dissipation in active and idle modes

 Higher Performance 10%–25% higher bench-

mark performance than the original Intel387 SX

Math CoProcessor

 High Performance 84-bit Internal Architecture

 Eight 80-bit Numeric Registers usable as individ-

ually addressable general registers or as a regis-

ter stack

 Full-range transcendental operations for SINE

COSINE TANGENT ARCTANGENT and LOG-

ARITHM

 Programmable rounding modes and notification

of rounding effects

 Exception reporting either by software polling or

hardware interrupts

 Fully compatible with the SX Microprocessors

 Expands Intel386 SX CPU data types to include

32-bit 64-bit and 80-bit Floating Point 32-bit and

64-bit Integers and 18 Digit BCD Operands

 Directly extends the Intel386 SX CPU Instruction

Set to trigonometric logarithmic exponential

and arithmetic functions for all data types

 Operates independently of Real Protected and

Virtual-86 Modes of the Intel386 SX Microproces-

sors

 Fully compatible with the Intel387 SL Mobile and

DX Math CoProcessors Implements all Intel387

Math CoProcessor architectural enhancements

over 8087 and 80287

 Implements ANSI IEEE Standard 754-1985 for

binary floating point arithmetic

 Upward Object Code compatible from 8087 and

80287

2 2 Math CoProcessor Architecture

As shown in Figure 2-1 the Intel387 SX Math Co-

Processor is internally divided into four sections the

Bus Control Logic the Data Interface and Control

Logic the Floating Point Unit and the Power Man-

agement Unit The Bus Control Logic is responsible

for the CPU bus tracking and interface The Data

Interface and Control Unit latches data and decodes

instructions The Floating Point Unit executes the

mathematical instructions The Power Management

Unit is new to the Intel387 family and is the nucleus

Figure 2-1 Intel387TM SX Math CoProcessor Block Diagram

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