89C51CC03UA-UM 데이터 시트보기 (PDF) - Atmel Corporation

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89C51CC03UA-UM

Enhanced 8-bit MCU with CAN Controller and Flash Memory

Atmel Corporation 

Figure 3. Port 2 Structure

ADDRESS HIGH/ CONTROL

READ

LATCH

1

INTERNAL

BUS

D

Q

0

P2.X

WRITE

TO

LATCH

LATCH

VDD

INTERNAL

PULL-UP (2)

P2.x (1)

READ

PIN

Notes:

1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus

drivers.

2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for

memory bus cycle.

When Port 0 and Port 2 are used for an external memory cycle, an internal control signal

switches the output-driver input from the latch output to the internal address/data line.

Read-Modify-Write

Instructions

Some instructions read the latch data rather than the pin data. The latch based instruc-

tions read the data, modify the data and then rewrite the latch. These are called "Read-

Modify-Write" instructions. Below is a complete list of these special instructions (see

Table ). When the destination operand is a Port or a Port bit, these instructions read the

latch rather than the pin:

Instruction

ANL

ORL

XRL

JBC

CPL

INC

DEC

DJNZ

MOV Px.y, C

CLR Px.y

SET Px.y

Description

logical AND

logical OR

logical EX-OR

jump if bit = 1 and clear bit

complement bit

increment

decrement

decrement and jump if not zero

move carry bit to bit y of Port x

clear bit y of Port x

set bit y of Port x

Example

ANL P1, A

ORL P2, A

XRL P3, A

JBC P1.1, LABEL

CPL P3.0

INC P2

DEC P2

DJNZ P3, LABEL

MOV P1.5, C

CLR P2.4

SET P3.3

It is not obvious the last three instructions in this list are Read-Modify-Write instructions.

These instructions read the port (all 8 bits), modify the specifically addressed bit and

10 AT89C51CC03

4182K–CAN–05/06

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