89C51CC03UA-UM 데이터 시트보기 (PDF) - Atmel Corporation

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89C51CC03UA-UM

Enhanced 8-bit MCU with CAN Controller and Flash Memory

Atmel Corporation 

Pin Name

RESET

ALE

PSEN

EA

XTAL1

XTAL2

Type Description

Reset:

I/O A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down

resistor to VSS permits power-on reset using only an external capacitor to VCC.

ALE:

O

An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is

activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are

executed from an internal Flash (EA = 1), ALE generation can be disabled by the software.

PSEN:

The Program Store Enable output is a control signal that enables the external program memory of the bus during external

O fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when

executing from of the external program memory two activations of PSEN are skipped during each access to the external Data

memory. The PSEN is not activated for internal fetches.

EA:

I When External Access is held at the high level, instructions are fetched from the internal Flash. When held at the low level,

AT89C51CC03 fetches all instructions from the external program memory.

XTAL1:

I

Input of the inverting oscillator amplifier and input of the internal clock generator circuits.

To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate

above a frequency of 16 MHz, a duty cycle of 50% should be maintained.

O

XTAL2:

Output from the inverting oscillator amplifier.

I/O Configurations

Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A

CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A

CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a

"read pin" signal transfers the logical level of the Port pin. Some Port data instructions

activate the "read latch" signal while others activate the "read pin" signal. Latch instruc-

tions are referred to as Read-Modify-Write instructions. Each I/O line may be

independently programmed as input or output.

Port 1, Port 3 and Port 4

Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external

source can pull the pin low. Each Port pin can be configured either for general-purpose

I/O or for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register.

This turns off the output FET drive.

To configure a pin for its alternate function, set the bit in the Px register. When the latch

is set, the "alternate output function" signal controls the output level (see Figure 1). The

operation of Ports 1, 3 and 4 is discussed further in the "quasi-Bidirectional Port Opera-

tion" section.

8 AT89C51CC03

4182K–CAN–05/06

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