WM8768 데이터 시트보기 (PDF) - Cirrus Logic

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WM8768

24-bit, 192kHz 8-Channel DAC

Cirrus Logic 

WM8768

MASTER CLOCK TIMING

MCLK

t MCLKL

tMCLKH

t MCLKY

Production Data

Figure 1 DAC Master Clock Timing Requirements

Test Conditions

AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless

otherwise stated.

PARAMETER

SYMBOL

System Clock Timing Information

MCLK System clock pulse width

high

tMCLKH

MCLK System clock pulse width

low

tMCLKL

MCLK System clock cycle time

MCLK Duty cycle

tMCLKY

Power-saving mode activated

Normal mode resumed

Table 1 Master Clock Timing Requirements

TEST CONDITIONS

After MCLK stopped

After MCLK re-started

MIN

11

11

28

40:60

2

0.5

TYP

MAX

UNIT

1000

60:40

10

1

ns

ns

ns

Us

MCLK

cycle

Note:

If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with

internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be

accessed in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically

powered up, but a write to the volume update register bit is required to restore the correct volume settings.

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

WM8768

DAC

LRCLK

DIN1/2/3/4

4

DSP/

DECODER

Figure 2 Audio Interface - Master Mode

w

PD Rev 4.3 July 2010

8

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