WM8956 데이터 시트보기 (PDF) - Cirrus Logic

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WM8956

Hi-Fi DAC with 1W Stereo Class D Speaker Drivers and Headphone Drivers

Cirrus Logic 

Production Data

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

WM8956

MCLK

tMCLKY

Figure 2 System Clock Timing Requirements

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA = +25oC

PARAMETER

System Clock Timing Information

MCLK cycle time

MCLK duty cycle

SYMBOL

TMCLKY

TMCLKDS

CONDITIONS

MIN

33.33

60:40

TYP

MAX

40:60

UNIT

ns

AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

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PD, November 2011, Rev 4.1

11

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