M12L128324A-5BG2E 데이터 시트보기 (PDF) - [Elite Semiconductor Memory Technology Inc.

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M12L128324A-5BG2E

1M x 32 Bit x 4 Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

(Preliminary)

M12L128324A (2E)

AC CHARACTERISTICS (AC operating condition unless otherwise noted)

Parameter

CAS latency = 3

CLK cycle time

CAS latency = 2

CLK to valid

output delay

CAS latency = 3

CAS latency = 2

Output data

hold time

CAS latency = 3

CAS latency = 2

CLK high pulse width

CLK low pulse width

Input setup time

Input hold time

CLK to output in Low-Z

CLK to output

in Hi-Z

CAS latency = 3

CAS latency = 2

Symbol

tCC

tSAC

tOH

tCH

tCL

tSS

tSH

tSLZ

tSHZ

-5

Min

Max

5

1000

8.6

4.5

6

2

2

2

2

1.5

1

1

4.5

6

-6

Min

Max

6

1000

8.6

5.5

6

2

2

2

2

2

1

1

5.5

6

-7

Unit Note

Min

Max

7

1000 ns

1

8.6

6

ns 1,2

6

2

ns

2

2

2.5

ns

3

2.5

ns

3

2

ns

3

1

ns

3

1

ns

2

6

ns

-

6

Note:

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.

3. Assumed input rise and fall time (tr & tf) =1ns.

If tr & tf is longer than 1ns transient time compensation should be considered.

i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.

Elite Semiconductor Memory Technology Inc.

Publication Date: Jun. 2011

Revision: 0.1

6/44

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