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DS1200-3-003 데이터 시트보기 (PDF) - Artesyn Technologies

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DS1200-3-003
ARTESYN
Artesyn Technologies ARTESYN
DS1200-3-003 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
Embedded Power for
Business-Critical Continuity
Electrical Specifications
CONTROL AND STATUS SIGNALS
Input Signals
PSON_L
Active LOW signal which enables/disables the main output. Pulling this signal LOW will turn-on the main output.
A 100pF decoupling capacitor is recommended at the system side.
MIN
MAX
VIL Input logic level LOW
VIH Input logiv level HIGH
2.0V
ISOURCE Current that may be sourced by this pin
ISINK Current that may be sunk by this pin at low state
PSKILL_L
0.8V
5.0V
2mA
0.5mA
First break/Last Mate active LOW signal which enables/disables the main output. This signal will have to be pulled to ground at the system side with a 220ohm resis-
tor. A 100pF decoupling capacitor is also recommended.
MIN
MAX
VIL Input logic level LOW
VIH Input logic level HIGH
2.0V
ISOURCE Current that may be sourced by this pin
ISINK Current that may be sunk by this pin at low state
VSENSE+, VSENSE-, STBY_VSENSE+
0.8V
5.0V
2mA
0.5mA
VSENSE+, VSENSE-, and STBY_VSENSE+ lines are the remote sense lines for regulation. Each line will compensate for a maximum of 100mV.
RReevv.. 0019..1216..0183
DSD1S20102H00E
33 ooff 49
Output Signals
ACOK_L
Signal used to indicate the presence of AC input to the power supply. A logic level LOW will indicate that the AC input to the power supply is within the operating range
while a logic level HIGH will indicate that AC has been lost.
This is an open collector/drain output. This pin is pulled high by a 1.0kohm resistor connected to 3.3V inside the power supply. It is recommended that this pin be
connected to a 100pF decoupling capacitor and pulled down by a 100kohm resistor at the system side.
MIN
MAX
VIL Output logic level LOW
0.6V
VIH Output logic level HIGH
2.0V
5.0V
ISOURCE Current that may be sourced by this pin
3.3mA
ISINK Current that may be sunk by this pin at low state
0.7mA
PWR_GOOD / PWOK_H
"Signal used to indicate that main output voltage is within regulation range. The PWR_GOOD/PWOK_H signal will be driven HIGH when the output voltage is valid and
will be driven LOW when the output falls below the under-voltage threshold.
This signal also gives an advance warning when there is an impending power loss due to loss of AC input or system shutdown request. More details in the Timing
Section. This is an open collector/drain output. This pin is pulled high by a 1.0kohm resistor connected to 3.3V inside the power supply. It is recommended that this
pin be connected to a 100pF decoupling capacitor and pulled down by a 10kohm resistor."
MIN
MAX
VIL Output logic level LOW
VIH Output logic level HIGH
2.0V
ISOURCE Current that may be sourced by this pin
ISINK Current that may be sunk by this pin
0.8V
5.0V
3.3mA
0.7mA

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