CAT24C208(2009) 데이터 시트보기 (PDF) - ON Semiconductor
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CAT24C208 Datasheet PDF : 10 Pages
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CAT24C208
Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 2.5 V to 5.5 V, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Typ
ICC
ISB
ILI
ILO
VIL
VIH
VHYS
Power Supply Current
Standby Current (VCC = 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Hysteresis
fSCL = 100 KHz
VIN = GND or either DSP or DDC VCC
VIN = GND to either DSP or DDC VCC
VOUT = GND to either DSP or DDC VCC
−1
VCC x 0.7
0.05
VOL1
VCCL1
VCCL2
Output Low Voltage (VCC = 3 V)
Leakage DSP VCC to DDC VCC
Leakage DDC VCC to DSP VCC
IOL = 3 mA
Max
3
50
10
10
VCC x 0.3
VCC + 0.5
0.4
±100
±100
Units
mA
mA
mA
mA
V
V
V
V
mA
mA
Table 6. A.C. CHARACTERISTICS (VCC = 2.5 V to 5.5 V, unless otherwise specified.)
Symbol
Parameter
READ & WRITE CYCLE LIMITS
FSCL
TI (Note 6)
tAA
tBUF (Note 6)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR (Note 6)
tF (Note 6)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Min
Max
Units
400
kHz
100
ns
0.9
ms
1.3
ms
0.6
ms
1.3
ms
0.6
ms
0.6
ms
0
ns
100
ns
300
ns
300
ns
0.6
ms
100
ns
Table 7. POWER−UP TIMING (Notes 6 and 7)
Symbol
Parameter
Min
Typ
Max
tPUR
Power−up to Read Operation
1
tPUW
Power−up to Write Operation
1
6. This parameter is tested initially and after a design or process change that affects the parameter.
7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 8. WRITE CYCLE LIMITS
Symbol
tWR
Parameter
Write Cycle Time
Min
Typ
Max
5
Units
ms
ms
Units
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond
to its slave address.
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