CAT24C208 데이터 시트보기 (PDF) - ON Semiconductor
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CAT24C208 Datasheet PDF : 11 Pages
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CAT24C208
Functional Description
The CAT24C208 has a total memory space of 1K bytes
which is accessible from either of two I2C interface ports,
(DSP_SDA and DSP_SCL) or (DDC_SDA and
DDC_SCL), and with the use of segment pointer at address
60h. On power up and after any instruction, the segment
pointer will be in segment 00h for DSP and in segment 00h
of the bank selected by the configuration register for DDC.
The entire memory appears as contiguous memory space
from the perspective of the display interface (DSP_SDA and
DSP_SCL), see Figure 4, and Figures 14 to Figure 21 for a
complete description of the DSP Interface.
A configuration register at addresses 62/63h is used to
configure the operation and memory map of the device as
seen from the DDC interface, (DDC_SDA and DDC_SCL).
Read and write operations can be performed on any
location within the memory space from the display DSP
interface regardless of the state of the EDID SEL pin or the
activity on the DDC interface. From the DDC interface, the
memory space appears as two 512 byte banks of memory,
with 2 segments each 00h and 01h in the upper and lower
bank, see Figure 3.
Each bank of memory can be used to store an E−EDID
data structure. However, only one bank can be read through
the DDC port at a time. The active bank of memory (that is,
the bank that appears at address A0h on the DDC port) is
controlled through the configuration register at 62/63h and
the EDID_SEL pin.
No write operations are possible from the DDC interface
unless the DDC Write Enable bit is set (WE = 1) in the device
configuration register at device address 62h.
The device automatically arbitrates between the two
interfaces to allow the appearance of individual access to the
memory from each interface.
In a typical E−EDID application the EDID_SEL pin is
usually connected to the “Analog Cable Detect” pin of a
VESA M1 compliant, dual−mode (analog and digital)
display. In this manner, the E−EDID appearing at address
A0h on the DDC port will be either the analog or digital
E−EDID, depending on the state of the “Analog Cable
Detect” pin (pin C3 of the M1−DA connector). See Figure 2.
TO HOST
CONTROLLER
28
DDC +5V
47.5K
10K
C3
27
DDC CLK
26
DDC DATA
+5V DC
(SUPPLIED
BY DISPLAY)
8
1
7
6
E−EDID
EEPROM
2
3
5
4
I2C TO PROJECTOR/MONITOR
DISPLAY CONTROLLER
Fuse, Resistor or Other Current
Limiting Device Required in All
M1 Displays
8 HPD
2A MAX
RELAY CONTACTS SHOWN IN
DE−ENERGIZED POSITION
Figure 2.
MEMORY ARRAY
01
Segment 1
256 Bytes
Upper
Bank
00
Segment 0
00
256 Bytes
01
Segment 1
256 Bytes
Lower
Bank
00
Segment 0
00
256 Bytes
Segment Pointer
Address by Configuration
Register (see Table 10)
No Segment Pointer
Figure 3. DDC Interface
MEMORY ARRAY
11
Segment 3
256 Bytes
10
Segment 2
256 Bytes
01
Segment 1
256 Bytes
00
Segment 0
00
256 Bytes
Segment Pointer
No Segment Pointer
Figure 4. DSP Interface
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